Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2009-11-06
2011-12-20
Dinh, Son (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S185120
Reexamination Certificate
active
08081522
ABSTRACT:
Within a page buffer14which is coupled to a non-volatile memory cell array10and temporally stores data as the data with a predetermined page unit is written in and read out to/from the memory cell array10, at least one latch circuit14v-1including a bit line selector14s, a page buffer unit circuit14uincluding two latch L1, L2, and a latch L3is set up for a plurality of bit lines. The bit line selector14sselects one bit line and couples it to the page buffer unit circuit14u. The latch L1temporally stores the data which are read out from the memory cell of the selected bit line, and then outputs the data through the latch L2or L3. On the other hand, the latch L1temporally stores the programming data inputted through the latch L2or L3, and after that outputs it to the memory cell of the selected bit line for programming.
REFERENCES:
patent: 7379333 (2008-05-01), Lee et al.
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patent: 2001-028575 (2001-01-01), None
patent: 2003-346485 (2003-12-01), None
patent: 2006-269044 (2006-10-01), None
Dinh Son
Muncy Geissler Olds & Lowe, PLLC
Nguyen Nam
Powerchip Technology Corporation
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