Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-11-19
1998-07-14
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711154, 711206, G06F 1206, G06F 1210
Patent
active
057819220
ABSTRACT:
A first level (L1) memory cache is structured on page boundaries, allowing for dynamic allocation of N byte pages based upon program needs. The contents of the cache are accessed by first determining the page location by cache address translation and then indexing directly into the cache. A starting page address tag exists for each page in the cache. If the page address is contained in the current page lookup, the in-line data is directly fetched. Direct fetching without address lookup speeds up the cache access cycle. If the address is not a current page, then the page address lookup occurs to obtain the correct page address block index into the page data macro. If a miss occurs, a page reload follows.
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Braceras George M.
Goodnow Kenneth J.
Ventrone Sebastian T.
Chow Christopher S.
International Business Machines - Corporation
Schkurko, Esq. Eugene
Swann Tod R.
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