Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-11-07
2006-11-07
Torres, Joseph D. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S724000
Reexamination Certificate
active
07134059
ABSTRACT:
In a pad connection structure for a plurality of embedded memory devices in a system-on-a-chip configuration, common pads are separately allotted to signal lines of embedded memory devices used for identical purposes and corresponding multiplexers are connected between the common pads and the signal lines of the embedded memory devices, thereby significantly reducing the number of input and output pads of the memory merged logic, minimizing damage to the pads, as a result of low probing frequency, and sequentially testing the embedded memory devices in a single testing operation.
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Mills & Onello LLP
Samsung Electronics Co,. Ltd.
Torres Joseph D.
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