Packet type integrated circuit memory devices having pins assign

Details Packet type integrated circuit memory devices having pins assign Packet type integrated circuit memory devices having pins assign

1998-12-08

2000-06-20

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Testing

36523006, G11C 700

Patent

active

060785365

ABSTRACT:
An integrated circuit memory device and method including a direct mode assigns internal data and address signals to separate pins. In particular, a plurality of first pins is assigned to the plurality of internal data signals that provide the data to the memory array in direct test mode. A plurality of second pins is assigned to the plurality of internal address signals that provide the address to the memory array in direct test mode, wherein none of the pins included in first plurality of pins are included in the second plurality of pins.

REFERENCES:
patent: 4205373 (1980-05-01), Shah et al.
patent: 5473575 (1995-12-01), Farmwald et al.
patent: 5578940 (1996-11-01), Dillon et al.
patent: 5606717 (1997-02-01), Farmwald et al.
patent: 5663661 (1997-09-01), Dillon et al.
patent: 5799209 (1998-08-01), Chatter

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