Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2003-01-16
2003-11-11
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189011, C365S189020
Reexamination Certificate
active
06646928
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit (“IC”) dynamic random access memory (“DRAM”) devices. More particularly, the present invention relates to a packet-based DRAM memory device incorporating an on-chip row register cache which is functional to reduce overall data access latencies, especially with respect to “page misses”.
A new type of volatile random access memory devices has been recently introduced which uses low pin count interfaces operating at high clock rates to multiplex memory control, address, and data in and out of the chip. These so called “protocol-based” or “packet-based” memories have the benefit of delivering high potential bandwidth in a low-pin count single chip IC package. This approach is particularly interesting for small systems containing just a single processor component and a single memory device.
The Rambus® DRAM (“RDRAM™”, trademarks of Rambus, Inc., Mountain View, Calif.) was the first of several proposed packet-based DRAM devices. The most current version of this product was developed in conjunction with Intel Corporation, Santa Clara, Calif. and is called the Direct Rambus DRAM (or “DRDRAM”). See for example, Rambus® Technology Overview, Rambus, Inc., Aug. 23, 1999 and Direct RDRAM™ Advance Information 64/72-Mbit (256K×16/18×16 d) Rambus, Inc. Aug. 3, 1998, the disclosures of which are specifically incorporated herein by this reference. The Direct RDRAM has been optimized to allow concurrent command, address, and data packets to be transferred to improve the efficiency of the bus interface.
Nevertheless, the DRDRAM presents several operational limitations which prevent its optimum performance and cost effectiveness. Firstly, the DRDRAM architecture imposes significantly larger chip sizes than are found in traditional DRAM components. This size increase results from the need to multiplex and demultipex data and addresses at the bus interface. Specifically, the current DRDRAM embodiment has a relatively complex eight way multiplexer and demultiplexer interface to the external data bus. This level of multiplexing is determined by the external data bus size and pipelined data speed of the core DRAM memory banks. The 18 bit external data bus is specified at an 800 MHz data rate and the DRAM core must deliver a 1.6 GB/sec. bandwidth. Current DRAM cores can deliver a new data-word every 10 ns or a 100 MHz data rate. For this core, the internal DRAM bus must be eight times 18 bits (or 144 bits) to deliver the specified data rate.
Secondly, multiplexing address and data buses increases random access latency compared to synchronous DRAM (“SDRAM”). At 800 MHz, address packet delays are 10 ns and data packet delays for a 64 bit equivalent word are 5 ns. Consequently, every SDRAM random access parameter is degraded by 15 ns in Direct RDRAM.
Thirdly, standard DRAM core exhibits relatively long latency on same bank “page misses” which reduce bus efficiency. The standard DRAM core uses page mode operation, which means that data is held in the DRAM sense amplifiers during random access within a page. If a request for another page in the same bank occurs, the DRAM must precharge and then another row must be randomly accessed into the sense amps. This “page miss” can take on the order of 70 ns in current DRAM technology. A “page miss” greatly reduces bus efficiency and delivered bandwidth. The maximum bandwidth for the device is equal to four data words (64 bit) at 5 ns/data word, which is 20 ns for 32 bytes, or 1600 MB/sec. On the other hand, the worst case bandwidth (in the case of a “page miss”, Read-to-Read) is 77.5 ns (“page miss”) plus three data word (64-bit) times at 5 ns/data word which equals 92.5 ns for 32 bytes or 338 MB/sec. Thus, it can be seen that Direct RDRAM bus efficiency is reduced from 100% to 21% under continuous random “page misses” while delivered bandwidth is reduced from 1600 MB/Sec to 338 MB/Sec.
SUMMARY OF THE INVENTION
Enhanced Memory Systems, Inc., a subsidiary of Ramtron International Corporation, Colorado Springs, Colo. and assignee of the present invention, has long been a pioneer in defining low latency, high efficiency DRAM core architectures based on its proprietary EDRAM® core technology (EDRAM® is a registered trademark of Enhanced Memory Systems, Inc., Colorado Springs, Colo.). See for example, U.S. Pat. Nos. 5,699,317, 5,721,862, and 5,887,272, the disclosures of which are specifically incorporated herein by this reference, and which disclose certain implementations of the application of this technology to standard DRAM architectures.
Disclosed herein are extensions of this EDRAM technology implemented to enhance packet-based DRAM architectures, such as Direct RDRAM, to reduce the initial device latency, reduce “page miss” latency and reduce chip layout overhead by reducing bus sizes and the level of required multiplexing and demultiplexing.
In accordance with an embodiment of the present invention disclosed herein, a row register (or “cache”) and separate write path, or bus, are integrated into each DRAM bank. This enhanced DRAM architecture, improves DRAM latency parameters and pipeline burst rate. The row register holds “read” data during burst reads to allow hidden precharge and same bank activation to minimize “page miss” latency. The faster pipelined burst rate simplifies Rambus RDRAM multiplexer/demultiplexer logic and reduces internal data bus size by 50%.
Particularly disclosed herein is a packet-based integrated circuit device comprising at least one dynamic random access memory bank having associated row and column decoders for specifying memory locations therein in response to externally supplied row and column addresses. The device includes at least one sense amplifier circuit coupled to the column decoder for reading data from the memory bank, a row register coupled to the sense amplifier circuit for retaining at least a portion of the data read out from the memory bank, a multiplexer circuit coupling the row register to an external data bus for supplying the read out data thereon and a demultiplexer circuit coupling the external data bus to the sense amplifier circuit for supplying data applied to the external data bus to the memory bank.
REFERENCES:
patent: 6151236 (2000-11-01), Bondurant et al.
patent: 6181612 (2001-01-01), Wada
patent: 6262937 (2001-07-01), Arcoleo et al.
Enhanced Memory Systems Inc.
Hogan & Hartson L.L.P.
Nguyen Van Thu
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