Packet addressing programmable dual port memory devices and...

Details Packet addressing programmable dual port memory devices and... Packet addressing programmable dual port memory devices and...

2007-03-27

2007-03-27

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S219000, C365S220000, C365S221000, C365S239000, C365S230030, C365S238500, C365S189040

Reexamination Certificate

active

10937519

ABSTRACT:
In a packet addressing method, one or more memory blocks are selected from a plurality of memory blocks and one or more data I/O pads are selected from a plurality of data I/O pads via which data input or output to/from the selected memory blocks are loaded, memory cell data output from the selected memory blocks are sequentially output to the selected data I/O pads, and data input to the selected data I/O pads are sequentially input to the selected memory blocks, so that read and write operations are independently accomplished in each of data I/O pads. The data I/O width can be adjusted according to the word length which is selectively set up, and power consumption can be reduced due to partial activation of the memory block.

REFERENCES:
patent: 5450355 (1995-09-01), Hush
patent: 5726948 (1998-03-01), Hush et al.

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