Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2006-04-25
2006-04-25
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S678000
Reexamination Certificate
active
07034401
ABSTRACT:
A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330) are made in the semiconductor substrate (140) of the interposer (120). Conductive paths going through the through vias connect the first contact pads (136C) to the second contact pads (340). The dies (124) are attached to the interposer after the attachment of the interposer to the BT substrate. In sequential soldering operations, the solder hierarchy is maintained by dissolving some material (e.g. copper) in the solder during soldering to raise the solder's melting temperature. For example, all of the solders may initially have the same melting temperature, but each solder's melting temperature is increased during soldering to prevent the solder from melting in the subsequent soldering operations.
REFERENCES:
patent: 5391514 (1995-02-01), Gall et al.
patent: 6163456 (2000-12-01), Suzuki et al.
patent: 6175158 (2001-01-01), Degani et al.
patent: 6322903 (2001-11-01), Siniaguine et al.
patent: 6498074 (2002-12-01), Siniaguine et al.
patent: 6498381 (2002-12-01), Halahan et al.
patent: 6661088 (2003-12-01), Yoda et al.
patent: 6903443 (2005-06-01), Farnworth et al.
patent: 2001/0019178 (2001-09-01), Brofman et al.
patent: 2002/0036340 (2002-03-01), Matsuo et al.
patent: 2002/0048916 (2002-04-01), Yanagida
patent: 2002/0074637 (2002-06-01), McFarland
patent: 2002/0175421 (2002-11-01), Kimura
patent: 2003/0047798 (2003-03-01), Halahan
patent: 2003/0080437 (2003-05-01), Gonzalez et al.
patent: 2003/0116859 (2003-06-01), Hashimoto
patent: 2003/0199123 (2003-10-01), Siniaguine
patent: 195 31 158 (1997-02-01), None
patent: 0 193 128 (1986-09-01), None
patent: 08-236579 (1996-09-01), None
patent: WO 01/45476 (2001-06-01), None
Wang, C.H.; Holmes, A.S.; Gao, S. “Laser-Assisted Bump Transfer for Flip Chip Assembly,” 2000 IEEE Int'l Symp on Electronic Materials & Packaging, pp. 86-90.
Gektin, Vadim; Bar-Cohen, Avram; Witzman, Sorin “Coffin-Mason Based Fatigue Analysis of Underfilled DCAs,” 1998 IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part A, vol. 21, No. 4, Dec. 1998, pp. 577-584.
Tran, S.K.; Questad, D.L.; Sammakia, B.G. “Adhesion Issues in Flip-Chip on Organic Modules,” 1998 InterSociety Conference on Thermal Phenomena, pp. 263-268.
“Chapter 7: Wedge and Double Cantilever Beam Tests on a High Temperature Melt Processable Polymide Adhesive, TPER-BPDA-PA,” pp. 221-242.
“Flip Chip Bonding in Practice” Issue No. 7, Sep. 2001, The Micro Circuit Engineering Newsletter.
www.flipchips.com/tutorial27.html “Flipchips: Tutorial 27, Shaping Gold Stud Bumps” pp. 1-8.
Jordan, Jerry “Gold Stud Bump In Flip-Chip Applications,” 2002 Palomar Technologies, Inc.
Jasper, Jorg “Gold or Solder Chip Bumping, the choice is application dependent” Chip Interconnection, EM Marin, pp. 1-4.
Zama, Satoru; Baldwin, Daniel F; Hikami, Toshiya; Murata, Hideaki “Flip Chip Interconnect Systems Using Wire Stud Bumps and Lead Free Solder,” 2000 IEEE Electronic Components and Technology Conference, pp. 1111-1117.
Lu, H. and Bailey, C. “Predicting Optimal Process Conditions for Flip-Chip Assembly Using Copper Column Bumped Dies” School of Computing and Mathematical Sciences, 2002 IEEE, 2002 Electronics Packaging Technology Conference, pp. 338-343.
Wang, Tie; Tung, Francisca; Foo, Louis; and Dutta, Vivek “Studies on A Novel Flip-Chip Interconnect Structure—Pillar Bump” Advanpack Solutions Pte Ltd, 2001 IEEE, 2001 Electronic Components and Technology Conference.
Perfecto, Eric; Lee, Kang-Wook; Hamel, Harvey; Wassick, Thomas; Cline, Christopher; Oonk, Matthew; Feger, Claudius; McHerron, Dale, “Evaluation of Cu Capping Alternatives for Polymide-Cu MCM-D” IEEE, 2001 Electronic Components and Technology Conference.
Pang, John H.L.; Chong, D.Y.R.; Low T.H. “Thermal Cycling Analysis of Flip-Chip Solder Joint Reliability” IEEE Transactions on Components and Packaging Technologies, vol. 24, No. 4, Dec. 2001, pp. 705-712.
Painaik, Mandar; and Hurley, Jim “Process Recommendations for Assembly of Flip Chips Using No-Flow Underfill” Semiconductor Products, Technical Bulletin, www.cooksonsemi.com.
Ekstrom; Bjorn “Thin Film Silicon Substrates For Lead Frame Packages” Advancing Microelectronics—May/Jun. 2003, pp. 6-7.
Gilleo, Ken “Substrates for Flip Chips” “Flip Chips Technology” in Area Array Packaging Handbook—Manufacturing and Assembly; K Gillio, Editor; The McGraw-Hill Companies, Inc., New York, NY.
Maiwald, Werner “Soldering SMD's Without Solder Paste” http://www.midwestpcb.com/sales/Kehoe/maiwald.htm.
“Staychip; 2078E No-Flow Fluxing Underfill; For Solding Sn/Pb eutectic solder bumps to common pad metallizations Preliminary Technical Bulletin” Semiconductor Products, Technical Bulletin; Cookson Electronics.
“Technical Data Sheet: No-Clean Pin-Probe Testable Solder Paste: NC253” www.aimsolder.com.
“Design Notes: Understanding Ball Grid Array Packages” Electronics by Design, www.electronicsbydesign.com.au, issue 1997.10, pp. 1-4.
Sperling, Ed; Electronic News, Sep. 17, 2003.
“Introduction to Printed Wiring Boards” Netpack Education Pool, p. 1-18.
“Production Qualification Report: Select Qual B: Strand Substrate on MCM MQFP Qual” Amkor Technology, Date Released: Jun. 14, 2002.
“Strand is Closing the Enterprise” Strand Interconnect AB, Viggengatan5, SE-602 09 Norrkoping Sweden, www.strandinter.se.
“200mm Wafer Fab” Strand Interconnect, Partner for High Performance Electronics.
Guenin, Bruce M. “The Many Flavors of Ball Grid Array Packages” Electronics Cooling, Feb. 2002, pp. 1-7.
“HPMX-5001: Demonstration Circuit Board: Application Brief 102” Hewlett Packard, pp. 1-10.
Moon, K.W.; Boettinger, W.J.; Kattner, U.R.; Biancaniello, F.S.; Handwerker, C.A. “The Ternary Eutectic of Sn-Ag-Cu Colder Alloys” Metallury Division, Materials Science and Engineering Laboratory NIST Gaithersburg, MD 20899 USA.
U.S. Appl. No. 10/739,788, entitled “Integrated Circuits and Packaging Substrates With Cavities, and Attachment Methods Including Insertion of Protruding Contact Pads into Cavities,” Filed on Dec. 17, 2003.
U.S. Appl. No. 10/798,540, entitled “Attachment of Integrated Circuit Structures and Other Substrates to Substrates with Vias,” Filed on Mar. 10, 2004.
“Solving Soldering Hierarchy Problems by Metallurgy and Design” IBM Technical Disclosure Bulletin, IBM Corp. New York, US, vol. 33, no. 8, Jan. 1991, pp.298-299, XP000106967, ISSN: 0018-8689.
Halahan Patrick B.
Kao Sam
Savastiouk Sergey
MacPherson Kwok & Chen & Heid LLP
Potter Roy
Shenker Michael
Tru-Si Technologies Inc.
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