Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2001-09-28
2002-11-05
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S784000, C257S777000, C257S685000, C257S686000, C257S775000, C257S776000, C257S576000, C257S738000, C257S737000, C257S773000, C257S723000
Reexamination Certificate
active
06476506
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This relates to packaged semiconductors and more particularly to packaged semiconductors with a die having multiple rows of bond pads that couple to a carrier of the die.
2. Related Art
As geometries in semiconductors continue to shrink in size due to improvements in the technology for making semiconductors, the die sizes themselves often become smaller. As these die sizes become smaller the complexity of the integrated circuit does not decrease but may even increase. Thus, the number of pins required for the integrated circuit does not necessarily change and if the functionality actually increases then the number of pins is likely to increase as well. Thus, for a given functionality, the die size is becoming smaller or in the alternative, for a given die size, the functionality, and thus the pin out number, is getting greater. In either case, there is then a difficulty in efficiently achieving all of the pin outs to a user of the integrated circuit. The packaging technology that is common for complex integrated circuits requiring many pin outs is called Ball Grid Array (BGA). There may in fact be a pad limit for a given size of integrated circuit. If the number of pads (pin outs) exceeds the limit for a given die size, the integrated circuit is considered to be pad limited.
One of the ways this is done is with wire bonding to the top surface of the package substrate with balls on the bottom surface and the integrated circuit being on the top surface and wire bonded to the top surface. Vias run from the top surface to the bottom surface and then traces run from the vias to the balls on the bottom and from bond fingers to vias on the top surface. It is desirable for the packaged substrate to be as small as possible, and it is also desirable for the integrated circuit to be as small as possible. In order to achieve the connections required between the integrated circuit and the top surface by way of the bond fingers, there must be enough space between the wires that run from the integrated circuit die to the bond fingers. One of the techniques for getting all of the connections made is to stagger the bond pads in two rows. This provides more space between the wires, however, there is still a limitation on how tightly spaced even the staggered ones can be. Further the staggering requires that the bond pads be further apart than the minimum that could be achieved based on the manufacturing capability. Thus the space required for the bond pads, due to staggering, is greater than the minimum space allowed for bond pads. Some techniques to try to improve the ability to provide the needed pin outs have included using cavity techniques on the substrate so that the bond fingers are on different levels. This substantially raises the cost of the substrate. Further, this may not provide for more than two rows even then.
Thus, there is a need for the ability to provide wires between an integrated circuit and bond fingers on a package substrate in a manner that does not mandate a bond spacing greater than the minimum pitch requires and being able to provide the full number of pins required without having to increase the die size simply for the purpose of being able to achieve the needed wire bonding.
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Gerber Mark Allen
Miller Jean Desiree
O'Connor Shawn M.
Clingan, Jr. James L.
King Robert L.
Motorola Inc.
Williams Alexander O.
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