Packaged semiconductor device with dual exposed surfaces and...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents

Reexamination Certificate

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Details

C257S678000, C257S692000, C257S696000, C257S726000, C257S727000

Reexamination Certificate

active

07576429

ABSTRACT:
The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces.

REFERENCES:
patent: 6521982 (2003-02-01), Crowley et al.
patent: 6756658 (2004-06-01), Gillett et al.
patent: 6777786 (2004-08-01), Estacio
patent: 6777800 (2004-08-01), Madrid et al.
patent: 6870254 (2005-03-01), Estacio et al.
patent: 6891256 (2005-05-01), Joshi et al.
patent: 2004/0232545 (2004-11-01), Takaishi
patent: 2005/0001293 (2005-01-01), Estacio
International Searching Authority; International Search Report and Written Opinion; Mailed Apr. 1, 2008 in PCT/US06/62695 (12 pages).

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