Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Patent
1994-02-18
1995-04-11
Ledynh, Bot
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
257692, 257696, 257700, 257787, H01L 2328
Patent
active
054060281
ABSTRACT:
A packaged semiconductor device has a semiconductor chip and leads formed over the chip with an electrically insulating film interposed therebetween and a packaging material for sealing the chip and the inner lead portions of the leads. The electrically insulating film has such an area as to provide a peripheral portion not covered by parts of the inner lead portions of the leads for strengthening adherence of the electrically insulating film to the packaging material and to the chip. The electrically insulating film has a thickness substantially in a range from 80 .mu.m to 200 .mu.m for absorbing stress which may be produced in the packaged semiconductor device when subjected to variations of the ambient temperature. A stress absorption film may be formed between the electrically insulating film and the semiconductor chip for absorbing stress which may be produced in the packaged semiconductor device when subjected to variations of the ambient temperature.
REFERENCES:
patent: 4711700 (1987-12-01), Cusack
patent: 5053852 (1991-10-01), Biswas et al.
patent: 5068712 (1991-11-01), Murakami et al.
Proceedings of the 1988 Electronic Components Conference, May 9, 1988, pp. 552-557, "Volume Production of Unique Plastic Surface-Mount Modules for the IBM 80-ns 1-Mbit DRAM Chip by Area Wire Bond Techniques".
Amagai Masazumi
Anjoh Ichiro
Arita Junichi
Beng Lim T.
Chong Chai T.
Hitachi , Ltd.
Ledynh Bot
Texas Instruments Incorporated
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