Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-03-16
2000-10-17
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714733, 324 731, 324763, 324765, G01R 3128
Patent
active
061346853
ABSTRACT:
A method for partial parallel testing a plurality of integrated circuit packages using a multi-package tester head having a plurality of sockets. Each socket is used for testing an integrated circuit package. A first one of the sockets has a full complement of signal channels, and the other sockets have exclusive subsets of the full complement of signal channels. The first socket and the other sockets support parallel testing of the integrated circuit packages according to a first type of test. Only the first socket, with its full complement of signal channels, supports a second type of test. To test a plurality of integrated circuit packages, a group of packages are inserted in the sockets. A first-pass test is then performed, in parallel, on the packages in the sockets. Then, for packages that passed the first-pass test, second-pass testing is performed sequentially using the first socket.
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Advanced Micro Devices , Inc.
Moise Emmanuel L.
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