Package-free bonding pad structure

Details Package-free bonding pad structure Package-free bonding pad structure

1999-04-26

2000-02-29

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

257698, 257700, 257774, 257780, 257781, 257786, H01K 2348

Patent

active

060312939

ABSTRACT:
A package-free bonding pad structure on a silicon chip that includes a plurality of metal pads on the upper surface of the silicon chip and a passivation layer covering the upper surface of the silicon chip. The passivation layer has a plurality of open cavities directly above the metal pad areas for exposing a portion of each metal pad. Diameter of the open cavity gets smaller on approaching the upper surface of the passivation layer and grows bigger in the neighborhood of the metal pad area.

REFERENCES:
patent: 5289038 (1994-02-01), Amano
patent: 5726498 (1998-03-01), Licatta et al.
patent: 5814891 (1998-09-01), Hirano
patent: 5962918 (1999-10-01), Kimura
IBM Technical Disclosure "Flip Chip Assembly for Improved Thermal Performance", vol. 37 No. 07, Jul. 1994.
IBM Technical Disclosure "Flip Chip Terminal for Semiconductor Devices" vol. 21 No. 3, Aug. 1978.

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