Package for integrated circuits

Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type

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Details

257728, 257787, H01L 2302

Patent

active

055369065

ABSTRACT:
In one form of the invention, a package for integrated circuits and devices (42), (46) is disclosed, the package including: a package base (44), the base having a first top surface; a layer of material (43) on the first top surface of the base (44) wherein the material (43) is patterned to cover a portion of the base, and wherein the layer of material (43) forms a substrate having a second top surface; a microstrip transmission line (45) on the second top surface; and a plastic encapsulant (50), wherein the encapsulant covers the first top surface of the base.

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D. Darrow and S. Vilmer-Bagen, "A Comparative Analysis of Thin Film Metallization Methodologies for High Density Multilayer Hybrids", International Conference on Multi-Chip Modules, pp. 1-15, Apr. 1, 1992.
D. Darrow and S. Vilmer-Bagen, "Low-cost Patterned Metallization Technique for High Density Multilayer Interconnect Applications", Electronic Components and Technology Conference, pp. 544-549, Jun. 3, 1993.
M. Jadhav, S. Phadke, S. Gangal, and R. Karekar, "Electrical and Mechanical Properties of Ion-plated Copper Metallization on Dielectric Substrates", IEEE Trans. on Components, Hybrids and Manufacturing Technology, vol. 11, No. 2, Jun. 1988.

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