P-channel dynamic flash memory cells with ultrathin tunnel...

Static information storage and retrieval – Floating gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S263000, C438S264000, C257S315000

Reexamination Certificate

active

06888749

ABSTRACT:
Structures and methods involve dynamic enhancement mode p-channel flash memories with ultrathin tunnel oxide thicknesses. Both write and erase operations are performed by tunneling. The p-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will now be orders of magnitude faster than traditional p-channel flash memory. Structures and methods for p-channel floating gate transistors are provided that avoid p-channel threshold voltage shifts and achieve source side tunneling erase. The p-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms. The methods further include reading the p-channel memory cell by applying a potential to a control gate of the p-channel memory cell of less than 1.0 Volt.

REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 3882469 (1975-05-01), Gosney, Jr.
patent: 4173766 (1979-11-01), Hayes
patent: 4409723 (1983-10-01), Harari
patent: 4435785 (1984-03-01), Chapman
patent: 5020030 (1991-05-01), Huber
patent: 5408115 (1995-04-01), Chang
patent: 5596214 (1997-01-01), Endo
patent: 5740104 (1998-04-01), Forbes
patent: 5754477 (1998-05-01), Forbes
patent: 5768193 (1998-06-01), Lee et al.
patent: 5790455 (1998-08-01), Caywood
patent: 5796670 (1998-08-01), Liu
patent: 5801401 (1998-09-01), Forbes
patent: 5811865 (1998-09-01), Hodges et al.
patent: 5852306 (1998-12-01), Forbes
patent: 5886368 (1999-03-01), Forbes et al.
patent: 5959896 (1999-09-01), Forbes
patent: 5989958 (1999-11-01), Forbes
patent: 6008091 (1999-12-01), Gregor et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6025627 (2000-02-01), Forbes et al.
patent: 6031263 (2000-02-01), Forbes et al.
patent: 6063668 (2000-05-01), He et al.
patent: 6096640 (2000-08-01), Hu
patent: 6100559 (2000-08-01), Park
patent: 6204179 (2001-03-01), McTeer
patent: 6207222 (2001-03-01), Chen et al.
patent: 6222224 (2001-04-01), Shigyo
patent: 6245613 (2001-06-01), Hsu et al.
patent: 6246089 (2001-06-01), Lin et al.
patent: 6249460 (2001-06-01), Forbes et al.
patent: 6265266 (2001-07-01), Dejenfelt et al.
patent: 6297103 (2001-10-01), Ahn et al.
patent: 6316316 (2001-11-01), Wu
patent: 6319774 (2001-11-01), Hai
patent: 6351428 (2002-02-01), Forbes
patent: 6383939 (2002-05-01), Yang et al.
patent: 6456535 (2002-09-01), Forbes et al.
patent: 6515328 (2003-02-01), Yang et al.
patent: 6583011 (2003-06-01), Xia et al.
patent: 6605961 (2003-08-01), Forbes
patent: 6639835 (2003-10-01), Forbes
patent: 6720221 (2004-04-01), Ahn et al.
patent: 6730960 (2004-05-01), Forbes
patent: 20020016081 (2002-02-01), Aloni et al.
patent: 20020113262 (2002-08-01), Forbes
patent: 20030001197 (2003-01-01), Chang et al.
patent: 20030201491 (2003-10-01), Chung
Chen, I., et al., “A Physical Model for the Gate Current Injection in p-Channel MOSFET's”,IEEE Electron Device Letters, 14(5), 228-230, (May 1993).
Chen, J., et al., “Hot Electron Gate Current and Degradation in P-Channel SOI MOSFET's”,1991 IEEE International SOI Conference Proceedings, Vail Valley, Colorado, pp. 8-9, (Oct. 1991).
Chung, S.S., et al., “Performance and Reliability Evaluations of P-Channel Flash Memories with Different Programming Schemes”,International Electron Devices Meeting, Technical Digest, Washington, D.C., 295-298, (Dec. 1997).
Dipert, B., et al., “Flash Memory Goes Mainstream”,IEEE Spectrum, 30, 48-52, (Oct. 1993).
Ghodsi, R., et al., “Gate-Induced Drain-Leakage in Buried-Channel PMOS-A Limiting Factor in Development of Low-Cost, High-Performance 3.3-V, 0.25-um Technology”,IEEE Electron Device Letters, 19(9), 354-356, (Sep. 1998).
Ohnakado, T., et al., “1.5V Operation Sector-Erasable Flash Memory with BIpolar Transistor Selected (BITS) P-Channel Cells”,1998 Symposium on VLSI Technology; Digest of Technical Papers, 14-15, (1998).
Ohnakado, T., et al., “Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a P-Channel Cell”,1995 International Electron Devices Meeting Technical Digest, Washington D.C.,, pp. 279-282, (1995).
Ohnakado, T., et al., “Novel Self-Limiting Program Scheme Utilizing N-Channel Select Transistors in P-Channel DINOR Flash Memory”,1996 International Electron Devices Meeting Technical Digest, San Francisco, CA, pp. 181-184, (1996).
Papadas, C., et al., “Modeling of the Intrinsic Retention Charcteristics of Flotox EEPROM Cells Under Elevated Temperature Conditions”,IEEE Transaction on Electron Devices, 42, 678-682, (Apr. 1995).
Patel, N.K., et al., “Stress-Induced Leakage Current in Ultrathin SiO2 Films”,Appl. Phys. Letters, 64(14), 1809-1811, (Apr. 1994).
Salm, C., et al., “Gate Current and Oxide Reliability in p+ Poly MOS Capacitors with Poly-Si and Poly-Ge0.3Si0.7 Gate Material”,IEEE Electron Device Letters 19(7), (Jul. 1998).
Shi, Y., et al., “Tunneling Leakage Current in Ultrathin (<4 nm) Nitride/Oxide Stack Dielectrics”,IEEE Electron Device Letters, 19(10), pp. 388-390, (Oct. 1998).
Wu, Y., et al., “Time Dependent Dieletric Wearout (TDDW) Technique for Reliability of Ultrathin Gate Oxides”,IEEE Electron Device Letters, 20(6), 262-264, (Jun. 1999).
Chau, R., et al., “30nm Physical Gate Length CMOS Tansistors with 1.0 ps n-MOS and 1.7 ps p-MOS Gate Delays”,IEEE Int. Electron, Devices Meeting, San Francisco, (Dec., 2000),pp. 45-48.
Frank, J., et al., “Monte Carlo Simulations of p-and n-Channel Dual-Gate Si MOSFET's at the Limits of Scaling”,IEEE Transactions on Electron Devices, 40(11), (Nov. 1993),p. 2103.
Hirayama, M., et al., “Low-Temperature Growth of High-Integrity Silicon Oxide Films by Oxygen Radical Generated in High-Density Krypton Plasma”,IEEE, (1999),4 pages.
Ilyas, M., et al., “The optical absorption edge of amorphous thin films of silicon monoxide and of silicon monoxide mixed with titanium monoxide”,IEE, (2001), 1 page.
Muller, D. A., “The Electronic Structure at the Atomic Scale of Ultrathin Gate Oxides”,Nature, 399, (Jun. 1999),758-761.
Ohguro, T., “Tenth Micron P-MOSFET's with Ultra-Thin Epitaxial Channel Layer Grown by Ultra-High-Vacuum CVD”,Proceedings: International Electron.
Devices Meeting, IEEE, Washington, Dec. 5-8, 1993,(Dec. 5, 1993),pp. 433-436.
Strass, A., et al., “Fabrication and Characterisation of thin low-temperature MBE-compatible silicon oxides of different stoichiometry”,Thin Solid Films 349, (1999),pp. 135-146.
Tiwari, Sandip, “Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage”,Int'l Electron Devices Meeting: Technical Digest, Washington, DC,(Dec. 1995),521-524.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

P-channel dynamic flash memory cells with ultrathin tunnel... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with P-channel dynamic flash memory cells with ultrathin tunnel..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and P-channel dynamic flash memory cells with ultrathin tunnel... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3371394

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.