Ozone-enhanced oxidation for high-k dielectric semiconductor...

Details Ozone-enhanced oxidation for high-k dielectric semiconductor... Ozone-enhanced oxidation for high-k dielectric semiconductor...

2001-08-13

2003-06-03

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

C438S585000, C438S595000, C438S201000

Reexamination Certificate

active

06573193

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to CMOS device fabrication processes and, more particularly, to a method of manufacturing amorphous high dielectric constant film devices that are subject to oxidation processes at temperatures whereby crystallization of the amorphous high dielectric constant film is avoided.
BACKGROUND OF THE INVENTION
Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit involves numerous processing steps. A gate dielectric, typically formed from silicon dioxide, is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain. A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modern day processes employ features, such as gate conductors and interconnects, which have less than 1.0 micron critical dimension. As feature size decreases, the size of the resulting transistor as well as the interconnect between transistors also decreases. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
In semiconductor device fabrication, polysilicon and silicon dioxide are commonly used to form gate electrodes and gate dielectrics for metal-oxide-semiconductor (MOS) transistors. As device dimensions have continued to scale down, the thickness of the SiO
2
layer has also decreased to maintain the same capacitance between the gate and channel regions. A thickness of the gate oxide layer of less than 2 nanometers (nm) is expected in the future.
In order to achieve increased capacitance, gate oxide thickness has been reduced so much that current oxides are on the order of ten angstroms (1 nm) thick. Unfortunately, thin oxide films may break down when subjected to an electric field, particularly for gate oxides less than 50 Angstroms thick. It is probable that even for a relatively low gate voltage of 3V, electrons can pass through a thin gate oxide by what is known as the quantum mechanical tunneling effect. In this manner, a tunneling current may undesirably form between the semiconductor substrate and the gate conductor, adversely affecting the operability of the device. It is postulated that some of these electrons may become entrapped within the gate oxide by e.g., dangling bonds. As a result, a net negative charge density may form in the gate oxide. As the trapped charge accumulates with time, the threshold voltage V
T
may shift from its design specification. Breakdown of the gate oxide may also occur at even lower values of gate voltage, as a result of defects in the gate oxide. Such defects are unfortunately prevalent in relatively thin gate oxides. For example, a thin gate oxide often contains pinholes and/or localized voids due to unevenness at which the oxide grows on a less than perfect silicon lattice.
Because of high direct tunneling currents, SiO
2
films thinner than 1.5 nm cannot be used as the gate dielectric in CMOS devices. There are currently intense efforts to replace SiO
2
with high-k dielectrics, with TiO
2
and Ta
2
O
5
attracting the greatest attention. However, high temperature post deposition annealing treatments in the presence of oxygen to clean the film by oxidation of impurities and to fill oxygen vacancy defects (form oxide films) in the films (form oxide films) has been found to detrimentally affect high-k dielectric films by leading to crystallization of the film and formation of an interfacial SiO2 layer during the annealing treatment, make achieving an equivalent SiO2 thickness (EOT) of less than 1.5 nm very difficult. As will be appreciated, the high temperature oxygen anneal can cause oxygen to diffuse through the dielectric and form undesired silicon dioxide at the metal oxide/silicon nitride and/or at the silicon nitride/poly interfaces. Silicon dioxide formation at these interfaces will create a low dielectric constant film in series with the high dielectric metal oxide film and therefore reduce the effective capacitance of the film.
One solution to lowering the high tunneling current through thin gate oxide layers (typically SiO2) has been to use alternative high dielectric constant gate oxide materials. Materials with high dielectric constants permit gate dielectric layers to be made thicker, and so alleviate the tunneling current problem. While silicon dioxide (SiO2) has a dielectric constant of approximately 4, other materials have higher k (dielectric constant) values. Silicon nitride (“nitride”), for example, has a k of about 6 to 9 (depending on formation conditions). Much higher dielectric constant values of, for example, 20 or more can be obtained with various transition metal oxides including tantalum oxide (Ta
2
O5), barium strontium titanate (“BST”), and lead zirconate titanate (“PZT”). Using a high-k material for a gate dielectric would allow a high capacitance to be achieved even with a relatively thick dielectric. For example, a nitride gate dielectric having a thickness of 100 angstroms is substantially electrically equivalent to a silicon oxide gate dielectric having a thickness of about 50 angstroms. For even higher-k dielectrics, even thicker gate dielectrics could be formed while maintaining capacitance values higher than are possible with even very thin oxide layers. In this way, the reliability problems associated with very thin dielectric layers may be avoided while transistor performance is increased. These high-k dielectric films (high dielectric constant films) are defined herein as having a high dielectric constant relative to silicon dioxide. Typically, silicon dioxide has a dielectric constant of approximately 3.9, while high dielectric constant films have dielectric constants in the range of about 20 to 40.
Another problem associated with the above-mentioned high-k dielectrics is that, as mentioned, they may develop a crystalline structure under normal preparation conditions leading to a roughened film surface. Surface roughness causes non-uniform electrical fields in the channel region adjacent the dielectric film. Such films are not suitable for the gate dielectrics of MOSFET devices.
Despite their advantages, high-k materials pose IC fabrication challenges. For example, high-k material is relatively difficult to etch, unlike a conventional thermal oxide. Chemical etchants used with high-k materials may cause increased damage to associated oxide materials making high temperature rapid thermal oxidation processes necessary to repair such damage while leading to the undesirable effect of crystallization of an amorphous high-k dielectric film.
As a result, it would be advantageous if high-k dielectric films could be formed with reduced surface roughness, crystallinity, and electrical leakage. It would be advantageous if these non-crystalline high dielectric constant materials could be used in gate dielectrics and storage capacitors of integrated circuits. Possible solutions are to improve the thermal stability of the high-k dielectric films thereby avoiding film crystallization, or to provide processes whereby lower process temperatures (lower thermal budgets) are achieved. The thermal budget of a process is defined as the integral of device temperature T (t) over a fixed period of time.
High temperature processes that may be typically included in CMOS device manufacture include LDD (lightly doped drain) processes carried out at temperatures greater or equal to 900° C. and S/D (source/drain) activation carried out at greater or equal to 1000° C. More importantly, other processes may degrade high-k dielectric film properties such as poly-gate oxidation carried out at temperatures of about 1000° C.
Therefore it would be advantageous to develop a low temperature oxidation process whereby high-k dielectr

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