Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-09-29
2001-08-21
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S687000, C438S688000, C438S700000, C438S707000, C438S714000, C438S723000, C438S737000, C438S738000, C438S743000
Reexamination Certificate
active
06277733
ABSTRACT:
CROSS-REFERENCE TO RELATED PATENT/PATENT APPLICATIONS
The following commonly assigned patent/patent applications are hereby incorporated herein by reference:
Patent No./Serial No.
Filing Date
TI Case No.
60/066,568
November 26, 1997
TI-26189
60/066,590
November 29, 1997
TI-25250
60/103,455
October 6, 1998
TI-28051
FIELD OF THE INVENTION
The instant invention pertains to semiconductor device fabrication and processing and more specifically to post metal pattern and etch clean-up processing.
BACKGROUND OF THE INVENTION
Most semiconductor devices utilize multiple levels of metallization. With the increasing complexity of devices and the need to reduce the physical size of devices, the number of levels which incorporate metal connections is increasing. In addition, with the desire to increase the speed of the devices while reducing the power consumed by the devices, advanced metallization schemes are being developed. One such scheme involves the use of copper-doped aluminum or copper structures for the bus lines and interconnects. Additionally, interlevel dielectrics with lower dielectric constants than standard silicon dioxide films may be used as the dielectric material situated between metallic structures.
A problem that most semiconductor manufacturers face is the cleaning up of the metallic structures after the structures are patterned and etched. More specifically, the photoresist needs to be removed, and the residual metal halide etch byproducts have to be removed or converted to different chemical forms to avoid corrosion of the metal. These processes, commonly known as strip and passivation processes, may cause non-conducting residues to form on the metallic structure. In order to address this problem, a cleaning step is typically performed after the underlying metal structure is exposed and the photoresist is removed. The cleanup step will preferably remove all of the residue, typically comprised of polymers, that are formed on the metal structure, thus inhibiting corrosion of the metal structures. However, the clean step must not appreciably affect the electrical critical dimension (CD) of the metal structure.
For a typical Cu metallization scheme, a standard H
2
plasma strip process (see co-pending application Ser. No. 09/199,829, which is assigned to Texas Instruments) is performed to remove photoresist after a via oxide etch process. Since a photoresist strip with O
2
plasma causes substantial oxidation to any exposed Cu at the bottom of the via, this approach is generally not used. This is so even though a Si
3
N
4
barrier layer is present, and the via etch process completes to the Si
3
N
4
layer, without passing through the Si
3
N
4
layer. The nitride layer must then be removed in a separate wet or dry etch process. Thus, a dry plasma etch process which could be used to remove photoresist without oxidation of Cu would simplify the process flow by either eliminating the need for the Si
3
N
4
barrier layer, or substantially thinning it (it might still be useful as an etch stop layer for via formation). Removal or thinning of the Si
3
N
4
barrier layer would ease the oxide etch selectivity requirements since stopping the etch on the Si
3
N
4
layer would not be necessary.
SUMMARY OF THE INVENTION
An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a conductive structure over the substrate, the conductive structure comprised of an oxygen-sensitive conductor; forming a layer of dielectric material over the conductive structure; forming a photoresist layer over the layer of the dielectric material; patterning the layer of the dielectric material; removing the photoresist layer after patterning the layer of the dielectric material; and subjecting the semiconductor wafer to a plasma which incorporates the combination of hydrogen or deuterium and a fluorine-containing mixture which is comprised of a gas selected from the group consisting of: CF
4
, C
2
F
6
, CHF
3
, CFH
3
and other fluorine-containing hydrocarbon. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which includes hydrogen or deuterium, including NH
3
, N
2
H
2
, H
2
S, CH
4
or deuterated forms of these gases. The oxygen-sensitive material is, preferably, comprised of: copper, tantalum, tantalum nitride, titanium, titanium nitride, titanium silicide, tungsten, tungsten nitride, tungsten silicide, aluminum, copper-doped aluminum, silver, gold, ruthenium, ruthenium oxide, iridium, platinum, cobalt, cobalt silicide and any combination thereof. Preferably, the fluorine-containing mixture is around 2 to 10% of the combination (more preferably, around 4% of the combination). The step of subjecting the semiconductor wafer to a plasma which incorporates the combination of hydrogen or deuterium and a fluorine-containing mixture removes any exposed hydrocarbons formed over the semiconductor wafer and does not substantially remove any exposed nitride-containing structures.
REFERENCES:
patent: 5989997 (1999-11-01), Lin et al.
patent: 6107192 (2000-08-01), Subrahmanyan et al.
Brady III Wade James
Gurley Lynne A.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tsai Jey
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