Oxide formation process for manufacturing programmable logic...

Details Oxide formation process for manufacturing programmable logic... Oxide formation process for manufacturing programmable logic...

1999-01-08

2001-03-06

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S211000, C438S264000, C438S981000

Reexamination Certificate

active

06197638

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to methods of making programmable logic devices, and specifically electrically erasable programmable logic devices having a number of different transistor types on a single substrate.
2. Description of the Related Art
Programmable logic devices (PLD) are circuits which can be configured by a user to perform logic functions. Generally, PLDs include a programmable array of cells and array control circuitry which is utilized to program the array with the desired implementation. The programmable array comprises a series of low-voltage, short channel floating gate transistors which store charge to reflect whether a particular cell is programmed with a bit of data. The programmed array reflects in a particular user's individual configuration for the programmable device, allowing users to customize the programmable logic device for a number of different applications.
One type of programmable logic device which has become popular due to its performance and cost characteristics are electrically erasable (E
2
) CMOS programmable devices.
Erasable CMOS technology is based on the concept of a stored charge on a floating gate. Electrons are transferred to the gate through a physical mechanism known as Fowler-Nordheim tunneling. For an electrically erasable cell, a tunnel oxide is present between the source and drain regions and the floating gate that is about one-third of the thickness of a traditional transistor gate oxide. Fowler-Nordheim tunneling involves placing a potential across the tunnel oxide which distorts the electric field and allows electrons to traverse the tunnel oxide upon which they become trapped on a floating gate.
A schematic representation of an prior art programming cell in a programmable logic device is shown in FIG.
1
.
FIG. 2
shows a semiconductor cross-section of the programming cell shown in FIG.
1
. The control circuitry of the cell—the program transistors—essentially comprise high voltage transistors capable of sustaining high electric fields. As shown in
FIG. 2
, the read transistor, which operates at low voltage, includes a first junction
10
, second junction
12
and gate
14
, (defined by the word line), which is separated from the first and second junctions by oxide layer
20
. Oxide layer
20
has a thickness of approximately
150
A. Program transistor
32
includes a first junction
16
, second junction
18
and a gate
142
which also rests on oxide layer
20
. Floating gate
40
is separated from program junction
18
by tunnel oxide
22
which may be activated by control gate
24
, which has an underlying oxide thickness of about 180 Å. The thickness of tunnel oxide
22
is in a range of approximately 80-100 Å.
When programming or erasing the device, a voltage is applied between the program and control gate nodes. The direction of the voltage determines whether the cell is erased or programmed. When erasing, the control gate is given a positive voltage and the program node is grounded. When programming, the program node voltage is elevated and the control gate is grounded.
It should be generally recognized that several alternative designs of memory cells may be utilized. Characteristically, in an E
2
CMOS PLD, four types of transistors are required: high voltage P channel, high voltage N channel, low voltage P channel, and low voltage N channel. Techniques for saving mask steps during the formation of these cells are advantageous as each mask savings reduces the cost of the overall device.
The trend of E PLD devices has been toward lower and lower supply voltages. Consequently, this has required a corresponding scaling down of the gate oxide and two different oxide thicknesses for the gate and tunnel oxides. As the gate oxide thicknesses have been scaled down, they have begun to approach the thickness of the tunnel oxide on lightly or undoped silicon.
Traditionally, the manufacturing process for implementing all four types of cells requires a large number of sequential process steps. Generally, four separate masking steps were required to complete the formation of the tunnel regions and overlying oxides for the four different types of devices.
U.S. patent application Ser. No. 08/664,190 discloses a scheme for reducing the number of masks required for forming the transistors from four to three. The benefit of this is the savings of a mask step, but the process contemplates that the thickness of the tunnel region mask and either the n-channel or p-channel low voltage transistor will be roughly the same. If different oxide thicknesses are desired for the tunnel region and programming and the low voltage transistor, this method is of limited utility. What is required is a method which is capable of allowing flexibility in the formation of oxides for E
2
PLD devices with a minimum number of mask steps.
SUMMARY OF THE INVENTION
The invention, briefly described, comprises a process for forming a plurality of CMOS transistors on a semiconductor substrate, wherein the plurality of transistors includes high-voltage N-channel and high-voltage P-channel transistors, and low-voltage N-channel and low-voltage P-channel transistors, wherein a tunnel oxide of a first thickness is required and a gate oxide of a second thickness is required. The formation of multiple oxide regions of varying thicknesses is supported by the method of the present invention.
In accordance with the present invention, a method of providing oxide layers on the surface of a semiconductor substrate is provided. The method comprises the steps of: depositing a layer of nitride on the surface of the semiconductor substrate; etching a first and second portions of the nitride layer; forming a first and second regions of a first oxide layer on the substrate in the first and second etched portions of the nitride layer; etching a the first region of the oxide; forming a second oxide layer on the substrate having a first portion in the first etched portion of the nitride and a second portion overlying the first portion of the second region of the first oxide layer; removing the nitride layer; and forming a third layer of oxide having a first portion on the surface of the substrate, a second and third portions on the first and second portions of the second oxide layer.


REFERENCES:
patent: 5830795 (1998-11-01), Mehta et al.
patent: 5960274 (1999-09-01), Mehta
“Inside AMD's CMOS PLD Technology,” PLD DAtabook, AMD, 1993.
U.S. application No. 09/232,061, Fong et al., filed Jan. 15, 1999.

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