Oxidation and etchback process for forming thick contact area on

Details Oxidation and etchback process for forming thick contact area on Oxidation and etchback process for forming thick contact area on

1997-12-09

2000-02-22

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438586, H01L 218247

Patent

active

060279737

ABSTRACT:
A NAND type flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of memory cells which each include a floating gate for storing charge when the cell is programmed. Select lines are used to control programming, reading and erasing of the cells. The floating gates and the select line are integrally formed from a first polysilicon layer (POLY 1). A contact area of the select line which is used to make external connection through a vertical interconnect (via) is made thicker than the floating gates to avoid punchthrough of the contact area during a dry etching step which is used to form the via. The POLY 1 layer is first formed to an initial thickness, and a silicon nitride mask layer is formed over the POLY 1 layer. The portion of the silicon nitride layer over the contact area is protected with photoresist, and the remaining area of the silicon nitride layer is etched away. A predetermined surface thickness of the POLY 1 layer is oxidized to form silicon dioxide, and the silicon dioxide is etched away using an etchant which has a low, preferably zero etch rate for polysilicon, such that the thickness of the polysilicon layer except in the contact area which is protected by the silicon nitride mask layer is reduced. The thinned polysilicon layer is then patterned to form the select lines and the floating gates.

REFERENCES:
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patent: 5472892 (1995-12-01), Gwen et al.
patent: 5476814 (1995-12-01), Ohshima et al.
Wolf, "Silicon Processing for the VLSI Era", vol. 1, Process Technology, pp. 182-183, 198-199, 518, 529-534, 539-541, 581-582, 1986.

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