Overlapping jumping window for SONET/SDH bit error rate...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate

Reexamination Certificate

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C714S799000, C714S807000

Reexamination Certificate

active

10755403

ABSTRACT:
A method of performing multiple parallel event accumulations. This method permits devices to implement SONET/SDH Bit Error Rate monitoring on a large number of paths, but at a significantly lower cost of implementation than would be possible using existing approaches. The method removes the need for each path being monitored to have a time reference (frame counter) of its own. Instead, each monitoring path has two accumulators whose active regions will overlap in time such that the total number of frames covered will be a power of 2. This approach allows one global frame counter to be used for all the paths in question, even if those paths have completely different accumulation periods. This method of performing BER tests allows devices to perform such operations on thousands of tributary paths (VT, TU), rather than only on the STS-n/STM-n paths that most current SONET/SDH devices support.

REFERENCES:
patent: 5606563 (1997-02-01), Dorbolo et al.
patent: 6310911 (2001-10-01), Burke et al.
patent: 6738395 (2004-05-01), Diaconescu et al.
patent: 2006/0159089 (2006-07-01), Diaconescu et al.

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