Output enable access for an output buffer

Details Output enable access for an output buffer Output enable access for an output buffer

1994-10-05

1997-02-04

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 58, 326 88, H03K 1716

Patent

active

056002610

ABSTRACT:
The generation of a controlled voltage signal as a buffer control signal for an output driver provides for relatively less delay for a high output enable access for an output buffer. As the output buffer undergoes the transition from a deselected state to a selected state to generate an output signal corresponding to a high input signal, a first voltage level is generated at a node and output as the control signal for the output driver, providing for an initial pull-up transition for the output signal. A second voltage level is subsequently generated at the node and output as the control signal for the output driver, providing for a steady-state voltage level for the high output signal.

REFERENCES:
patent: 4703203 (1987-10-01), Gallup
patent: 4818901 (1989-05-01), Young
patent: 5047669 (1991-09-01), Iwamura
patent: 5081374 (1992-01-01), Davis
patent: 5151621 (1992-09-01), Goto
patent: 5329186 (1994-07-01), Hush et al.
patent: 5367205 (1994-11-01), Powell
patent: 5381059 (1995-01-01), Douglas

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