Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2006-09-29
2009-06-09
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S027000, C326S086000, C326S087000, C327S112000, C327S264000
Reexamination Certificate
active
07545164
ABSTRACT:
An output driver controls impedance using a mode register set. The output driver includes a main driving circuit that outputs and drives a main signal based on a data signal to a predetermined transmission line, an auxiliary driving circuit that outputs and drives an auxiliary signal to the transmission line, and a mode register set. The mode register set generates an impedance control signal group, a driving width control signal group and a delay control signal group. The amount of an auxiliary impedance (SIM), and the driving width and driving time point of an auxiliary signal (XSDR) can be controlled using the impedance control signal group, the driving width control signal group and the delay control signal group. Therefore, in accordance with the output driver of the present invention, the amount of output impedance (OIM), a pre-emphasis width and a pre-emphasis time point can be readily controlled, and the efficiency of the transmission of an output signal to a reception system is improved.
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Lee Jung Bae
Song In Dal
Crawford Jason
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
Tan Vibol
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