Output driver capable of controlling slew rate of output...

Details Output driver capable of controlling slew rate of output... Output driver capable of controlling slew rate of output...

2006-04-25

2006-04-25

Ho, Hoai (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S193000, C326S131000, C327S393000

Reexamination Certificate

active

07035148

ABSTRACT:
An output driver effectively controls the slew rate of an output signal according to CAS latency information including frequency information of an operating clock signal or according to frequency information obtained by detecting the frequency of the operating clock signal. The output driver includes an output terminal, a pull-up driver which pulls-up the output terminal, and a pull-down driver which pulls-down the output terminal. Also, the output driver further includes a mode register set (MRS) which stores CAS latency information of the semiconductor memory device. Driving capabilities of the pull-up driver and the pull-down driver are varied in response to the CAS latency information. The output driver may include a frequency detector which detects and stores the operating frequency of the semiconductor memory device. In this case, the driving capabilities of the pull-up driver and the pull-down driver are varied in response to output signals output from the frequency detector.

REFERENCES:
patent: 5220216 (1993-06-01), Woo
patent: 5783956 (1998-07-01), Ooishi
patent: 5917758 (1999-06-01), Keeth
patent: 6054885 (2000-04-01), Ooishi et al.
patent: 6362656 (2002-03-01), Rhee
patent: 6404258 (2002-06-01), Ooishi

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