Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1998-06-18
2000-01-18
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
365201, G01R 3128
Patent
active
060165618
ABSTRACT:
A memory system operable in a normal mode of operation and a test mode of operation includes sensing circuitry which generates x number of data bits during a read cycle. A read path circuit, coupled to the sensing circuitry, transfers the x number of data bits generated by the sensing circuitry during a first read cycle in the normal mode of operation to x number of output nodes. A first detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during a second read cycle in the test mode of operation are arranged in a pattern in which all bits are identical. A second detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are arranged in a pattern in which each two adjacent bits are different. An output circuit, coupled to the first and second detection circuits, generates y number of output data bits which are arranged in a pattern indicative of whether the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are identical, are arranged in a pattern in which each two adjacent bits are different, or are arranged in another pattern, and wherein y is less than x. A method of testing an integrated circuit (IC) memory is also disclosed.
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Cowan Gregory L.
Hawes Mark A.
Mowlavi Allahyar Vahidi
Roohparvar Fariborz F.
Micro)n Technology, Inc.
Nguyen Hoa T.
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