Output circuit for memory device

Details Output circuit for memory device Output circuit for memory device

1997-08-11

1998-11-24

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

326 27, 326 87, G11C 1604

Patent

active

058417028

ABSTRACT:
An output circuit for a semiconductor memory device includes an output buffer for buffering an externally applied output enable signal and a signal outputted from a sense amplifier in accordance with the output enable signal, and an output driver having a CMOS inverter structure connected between a supply voltage and a ground voltage. The output driver includes two pairs of MOS transistors, each having a transistor of a different channel size connected in parallel with each other. When the sense amplifier carries out a sensing operation, the larger channel size MOS transistors are driven by a voltage from a feedback output terminal. When the sensing operation is completed, both pairs of MOS transistors are simultaneously driven in accordance with an output signal of the output buffer. The circuit increases a data signal output speed and decreases the output noise, by turning the data output signal into a completely tri-stated signal during a sensing operation of the sense amplifier.

REFERENCES:
patent: 4961010 (1990-10-01), Davis
patent: 5036222 (1991-07-01), Davis
patent: 5192879 (1993-03-01), Aoki et al.
patent: 5315172 (1994-05-01), Reddy
patent: 5414672 (1995-05-01), Ozeki et al.
patent: 5424982 (1995-06-01), Kato
patent: 5517129 (1996-05-01), Matsui
patent: 5537060 (1996-07-01), Baek

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