Output circuit for an TTL-CMOS integrated circuit

Details Output circuit for an TTL-CMOS integrated circuit Output circuit for an TTL-CMOS integrated circuit

1995-05-01

1996-07-30

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326 58, 326 27, H03K 190175

Patent

active

055415334

ABSTRACT:
An output circuit for a TTL-CMOS integrated circuit that comprises an output stage with two P MOS and N MOS transistors in parallel, which are connected in cascade with an N MOS enabling transistor between the power supply and the reference voltages. The output stage connected by means of a validation signal TRISB and of P and N MOS transistors delivers an output signal representing the input logic variable to the common point between the P MOS transistor and enabling transistor. A first circuit allows switching of the P MOS transistor by an intermediate switching control signal TRISP and a third circuit allows switching of the N MOS transistor, the circuit operating in mode of feedback of the switching control of the P MOS transistor, the controls being applied successively in order to generate an intermediate switching level belonging to the high logic level.

REFERENCES:
patent: 4728822 (1988-03-01), Kusaka
patent: 5140195 (1892-08-01), Wakayama
patent: 5216299 (1993-06-01), Wanless
patent: 5418477 (1995-05-01), Dhong
Patent Abstracts of Japan, vol. 14, No. 336, 19 Jul. 1990, & JP-A-02 113 721 (Mitsubishi Electric Corp.).

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