Output circuit for alternating multiple bit line per column...

Details Output circuit for alternating multiple bit line per column... Output circuit for alternating multiple bit line per column...

1999-04-09

2001-04-24

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S051000, C365S154000, C365S230050

Reexamination Certificate

active

06222777

ABSTRACT:

BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to memories. More particularly, this invention relates to a new high speed memory circuit.
BACKGROUND OF THE INVENTION
As microprocessors operate at faster speeds, demand for faster memories continues to increase. In one memory application, a microprocessor uses a memory as a look-up table that stores a normalized set of coefficients representing a mathematical expression such as a quadratic equation or square root. These types of memories are typically read only memories (ROMs) and are referred to as coefficient ROMs.
Other memory applications use random access memories (RAMs) to temporarily store instructions and data. For example, the data can include a status array. Since RAMs perform reads and writes in the same cycle the timing and design constraints are greater.
In
FIG. 1
, a typical memory
20
has an array of memory cells
22
that store information, such as instructions and data, as digital information having a logical one or a logical zero value. A logical one corresponds to a high voltage level, while a logical zero corresponds to a low voltage level. To access information stored in the array of memory cells
22
, address signals, such as word line signals, are applied to the word lines
30
.
In response to the address signals on the word lines, the array of memory cells
22
outputs the stored information for a row of cells on a bus
36
to a column multiplexor
38
. In response to column select signals on a set
40
of column select lines
42
-
44
, the column multiplexor
38
outputs a voltage corresponding to a selected column on bus
46
. Typically, the voltage output by the column multiplexor
38
is very low and needs to be amplified for further processing. A sense amplifier
48
receives the signal on bus
46
and amplifies the signal to a predetermined level. In response to a sense amplifier enable signal, the sense amplifier outputs the amplified signals on yet another bus
50
.
FIG. 1
was described with respect to a single selected bit. To output a set of bits, such as a byte or a word, memories typically have a large memory array coupled to multiple column multiplexors. Each column multiplexor responds to the same set of column select lines and is associated with a separate sense amplifier.
FIG. 2
illustrates the memory of
FIG. 1
in more detail. The array
22
of memory cells (cell) has m rows
52
,
54
,
56
, and n columns,
62
,
64
,
66
. Each cell is connected to a bit line and a word line. Word line 0 (WL0)
32
, word line 1 (WL1)
33
and word line m−1 (WLm−1)
34
connect to the memory cells of rows
52
,
54
and
56
, respectively.
The memory cells in the array
22
output a differential signal. Therefore each bit line is associated with two traces or lines —a primary line
72
,
74
,
76
which carries one side of the differential signal and a complementary line
82
,
84
,
86
which carries the complement or other side of the differential signal. For example, Bit line 0 (BL0)
72
, Bit line 1 (BL1)
74
and Bit line n−1 (BLn−1)
76
and their complements {overscore (BL0+L )}
82
, {overscore (BL1+L )}
84
and {overscore (BLn−1+L )}
86
, connect to the memory cells of columns
62
,
64
, and
66
, respectively
All cells in a column connect to the same bit line, and all cells in a row connect to the same word line. For example, all cells in column
62
connect to lines
72
and
82
; and, all cells in row
52
connect to word line
32
. When the word line is enabled, the voltage stored in that cell is output on the respective bit line to the column multiplexor
38
.
In the column multiplexor
38
, passgate blocks
92
,
94
and
96
connect to columns
62
,
64
and
66
, respectively. In each passgate block
92
,
94
and
96
, PMOS transistors
102
,
103
,
104
,
105
,
106
and
107
, are connected in series with each bit line, BL0
72
, {overscore (BL0+L )}
82
, BL1
74
, {overscore (BL1+L )}
84
, BLn−1
76
and {overscore (BLn−1+L )}
86
, respectively. A column select signal, col
0
, col
1
and col n, is applied to the gates of the PMOS transistors of each passgate block
92
,
94
and
96
, respectively, which causes each passgate block
92
,
94
and
96
to output a differential signal. The differential outputs of the passgate blocks
92
,
94
and
96
, are connected and supplied to the sense amplifier
48
. Since only one column select signal, col
0
, col
1
and col n−
1
, is active at a time to select a column
62
,
64
,
66
, respectively, only one differential signal is applied to the sense amplifier
48
.
As shown in
FIG. 3
, one commonly used memory cell
110
has a pair of cross-coupled inverters,
112
,
114
, that act as a latch
116
to store a voltage representing a logical one or a logical zero. One end
118
,
120
of the latch
116
outputs a logical one while the other end,
120
,
118
, respectively, outputs the complement, a logical zero. In the memory cell
110
, the complementary signals output by the latch
116
are used as a differential signal on lines
118
and
120
to represent a logical one value or a logical zero.
A write port
121
is used to store data in the latch
116
. First and second access transistors, NMOS transistors
122
and
124
, respectively, connect to the latch
116
. The write word line
126
connects to the gate of each access transistor
122
,
124
. To store data in the memory cell, a write word line signal is asserted on the write word line
126
and a differential data signal is input via the NMOS access transistors,
122
and
124
, on the write bit lines
128
and
130
, respectively.
To sense the data, a read word line signal is asserted on the read word line
132
which is connected to the gates of a pair of NMOS passgate transistors
134
,
135
. The NMOS passgate transistors
134
,
135
form a read port
136
. The read word line signal is asserted by applying a predetermined voltage, such as a logical one, to the read word line
132
. In response to the assertion of the read word line signal, the end of the latch
116
storing a logical one (a high voltage level) will pull up the voltage of the associated line through one of the passgate transistors to the high voltage level (a logical one level). The end of the latch
116
storing a logical zero value (low voltage level) will pull down the voltage of the associated line through the other passgate transistor to the logical zero.
For example, if the latch
116
stores a logical one, when the read word line signal is asserted, read bit line
138
will be pulled up to a logical one, while read bit line
139
will be pulled down to a logical zero value. In contrast, if the latch
116
stores a logical zero value, when the read word line is asserted, read bit line
138
will be pulled down to a logical zero, while read bit line
139
will be pulled up to a logical one.
In memory circuits, capacitive effects reduce speed. One major capacitive effect is diffusion loading. NMOS and PMOS transistors have some amount of diffusion capacitance or diffusion loading. To form the source and drain of the transistors, the source and drain regions are doped with n+ and p+ ions, and these regions are referred to as diffusion regions. Diffusion regions have a diffusion capacitance between the diffusion region and the substrate. The amount of diffusion capacitance is related to the voltage between the diffusion regions and the substrate, as well as the effective area of the diffusion region and the depth of the diffusion region.
Referring back to
FIG. 2
, the diffusion loading of a particular bit line is related to the number of cells connected to that bit line. For example, bit line 0 (BL0)
72
connects to m cells. Therefore, if each cell has a diffusion capacitance of Cd, the total diffusion loading on the bit line 0 (BL0)
72
is Cd multiplied by m (m·Cd). The diffusion loading limits the speed at which the memory operates.
In the memory
20
of
FIG. 2
, a sense amplifier enable signal is used to co

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