Output circuit for a semiconductor memory device

Details Output circuit for a semiconductor memory device Output circuit for a semiconductor memory device

1983-09-02

1986-08-05

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365189, 307475, 307452, G11C 700, H03K 19092

Patent

active

046047310

ABSTRACT:
An output circuit for a semiconductor memory device including a preset circuit connected to a data output terminal and adapted to set a potential on the data output terminal to a potential between a potential of a first potential supply terminal and a potential of a second supply terminal during a preparative period for read preceding a data readout from a memory cell whereby the potential level on the data output terminal reaches a "H" level or a "L" level. Thus, the output circuit with high speed readout operation and with high reliability by means of being free from the instability caused by an output noise can be obtained.

REFERENCES:
patent: 3896430 (1975-07-01), Hatsukano
patent: 3942160 (1976-03-01), Yu
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4096584 (1978-06-01), Owen, III et al.
patent: 4397000 (1983-08-01), Nagami
patent: 4408135 (1983-10-01), Yuyama et al.
patent: 4465945 (1984-08-01), Yin
patent: 4491749 (1985-01-01), Iwamura

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