Output buffer with boost from voltage supplies

Details Output buffer with boost from voltage supplies Output buffer with boost from voltage supplies

1993-05-11

1995-11-21

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518911, 365194, G11C 700

Patent

active

054693853

ABSTRACT:
An MOS DRAM memory device includes an output buffer having an N-channel output transistor that must receive a boosted gate signal to produce a full Vdd output high logic level signal at the output terminal. The N-channel transistor connects between the Vdd supply voltage and the output terminal. The output buffer connects a Vdd supply voltage to the gate of the output transistor for a short period sufficient to raise the gate to the Vdd voltage level and then disconnects the Vdd supply. The buffer then connects a Vdd+ supply voltage to the gate to increase the gate voltage at least one transistor threshold value above the Vdd supply voltage. This provides the Vdd voltage at the output terminal.

REFERENCES:
patent: 4397000 (1983-08-01), Nagami
patent: 5057711 (1991-10-01), Lee et al.
patent: 5058066 (1991-10-01), Yu
patent: 5067109 (1991-11-01), Kim et al.
patent: 5241502 (1993-08-01), Lee et al.
patent: 5295098 (1994-03-01), Kohno
patent: 5311076 (1994-05-01), Park et al.
patent: 5331593 (1994-07-01), Merritt et al.

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