Output buffer for reducing slew rate variation

Details Output buffer for reducing slew rate variation Output buffer for reducing slew rate variation

2001-12-20

2003-06-24

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S027000, C326S057000, C326S081000

Reexamination Certificate

active

06583644

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present disclosure relates to a semiconductor integrated circuit, and more particularly, to an output buffer circuit of a semiconductor integrated circuit.
2. Description of the Related Art
In semiconductor integrated circuits, output buffer circuits are generally used to output internal data via an output terminal such as, for example, an output pad. As shown in
FIG. 1
, an output buffer circuit
10
includes an output driver
11
having a pull-up PMOS transistor P
11
and a pull-down NMOS transistor N
11
; a first inverter
13
that inverts output data D, applies the inverted output data to the gate of the pull-up PMOS transistor P
11
, and controls the pull-up slew rate of the output driver
11
; and a second inverter
15
that inverts the output data D, applies the inverted output data to the gate of the pull-down NMOS transistor N
11
, and controls the pull-down slew rate of the output driver
11
.
In the output buffer circuit
10
illustrated in
FIG. 1
, the slew rate of the output driver
11
is determined based on the current flow charging the load capacitance of an output terminal
17
through the pull-up PMOS transistor P
11
, and the current flow discharged from the load capacitance of the output terminal
17
through the pull-down NMOS transistor N
11
.
These currents, which affect the slew rate of the output driver
11
, vary considerably in the presence of process, voltage, and temperature (referred to as “PVT”) variations. Accordingly, the slew rate of the output driver
11
also varies considerably in the presence of PVT variations.
In addition, the slew rate of the output driver
11
varies depending on the magnitude of the load capacitance of the output terminal
17
. For example, if the load capacitance is increased by a factor of two, the slew rate of the output driver
11
generally increases by a corresponding factor of about two.
Unfortunately, in output buffer circuits such as, for example, that indicated by reference numeral
10
in
FIG. 1
, it is difficult to maintain a slew rate within a narrow tolerance under conditions in which the PVT and/or the load capacitance of the output terminal may vary.
SUMMARY OF THE INVENTION
These and other drawbacks and disadvantages are addressed by an output buffer for buffering output data while minimizing slew rate variations caused by PVT variations and/or changes in the load capacitance of an output terminal. Accordingly, an output buffer, usable in a semiconductor integrated circuit, is provided that includes a bias voltage generator for generating first and second bias voltages responsive to a reference voltage, an output driver in signal communication with the bias voltage generator for driving an output terminal, a first slew rate controller in signal communication with the output driver for controlling a pull-up slew rate of the output driver in response to the output data and the first bias voltage, a second slew rate controller in signal communication with the output driver for controlling a pull-down slew rate of the output driver in response to the output data and the second bias voltage, and a slew rate compensator in signal communication with the output ends of the first and second slew rate controllers and the output terminal for compensating for slew rate variation in response to a change in the load capacitance of the output terminal.
In a method of operation, the bias voltage generator generates first and second bias voltages using a reference voltage. The output driver drives an output terminal. The first slew rate controller controls the pull-up slew rate of the output driver in response to output data and the first bias voltage. The second slew rate controller controls the pull-down slew rate of the output driver in response to the output data and the second bias voltage. The slew rate compensator is connected to the output ends of the first and second slew rate controller and the output terminal and compensates for slew rate variation depending on the change in the load capacitance of the output terminal.
Preferred embodiments include those in which the output buffer circuit further includes a high voltage protector and a well voltage generator. If a voltage higher than a power supply voltage is applied to the output terminal, the high voltage protector drops the voltage and provides the dropped voltage to the output driver and the slew rate compensator. If a voltage higher than the power supply voltage is applied to the output terminal, the well voltage generator provides a voltage having substantially the same magnitude as the high voltage to the well of each PMOS transistor in the first and second slew rate controllers, the output driver, and the slew rate compensator.
These and other aspects, features and advantages of the present disclosure will become apparent from the following description of exemplary embodiments, which is to be read in connection with the accompanying drawings.


REFERENCES:
patent: 5066873 (1991-11-01), Chan et al.
patent: 5440258 (1995-08-01), Galbi et al.
patent: 6348814 (2002-02-01), Peterson

Affiliated with

Also associated with

Rating

Output buffer for reducing slew rate variation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Output buffer for reducing slew rate variation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Output buffer for reducing slew rate variation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3162103