Output buffer for external voltage

Details Output buffer for external voltage Output buffer for external voltage

2000-09-14

2001-07-24

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189110

Reexamination Certificate

active

06266284

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and, more particularly, to methods and systems for buffering electric signals to generate output signals with an external voltage in a flash electrically erasable programmable memory (“EEPROM”).
BACKGROUND
Computers, personal digital assistants, cellular telephones and other electronic systems and devices typically include processors and memory. The memory is used to store instructions (typically in the form of computer programs) to be executed and/or data to be operated on by the processors to achieve the functionality of the device. Some applications require retention of the instructions and/or data in a permanent or non-volatile storage medium. Such memories maintain information when the device is turned off or power is removed. Exemplary applications include computer Basic Input Output Systems (BIOS) storage and diskless handheld computing devices, such as personal digital assistants.
Flash memories store information in the absence of continuous power and are capable of being constructed in a very compact form. Flash memory is typically constructed by fabricating a plurality of floating gate transistors in a silicon substrate to form a core cell area. A floating gate transistor is capable of storing electrical charge on a separate gate electrode, known as a floating gate, that is separated by a dielectric layer from a control gate electrode. Generally, stored electrical charge in the floating gate represents a data state.
Flash memory devices also include a periphery area in the silicon substrate. Logic and addressing functions are performed by a plurality of logic and addressing circuits in the periphery area. The logic and addressing circuits perform internal logic operations such as reading, programming and erasing the stored charge in the floating gate transistors.
Flash memory devices also use a supply voltage (Vcc). The supply voltage (Vcc) is a fixed voltage power supply that is used to power the internal logic operations.
The flash memory is electrically interfaced with a system processor of an electronic system or device. To obtain data, the system processor directs the flash memory to perform a read operation. The flash memory operates the logic and addressing circuits to read the floating gate transistors and provides a plurality of outputs indicating whether the floating gate transistors are programmed or un-programmed (i.e. charge stored or not stored).
In general, an output buffer driver within the flash memory receives data signals read out from the flash memory and subsequently outputs data for use by the electronic system or device. Such an output buffer driver generally includes an output or final stage comprised of large-sized MOS transistors. Typically, the MOS transistors include a p-channel pull-up transistor and an n-channel pull-down transistor that cooperatively function to maintain the voltage level of the data output signal. The pull-up and pull-down transistors allow the output to be switched between logic high (logic “1”) and logic low (logic “0”) levels at high speed. The pull-up and pull-down transistors are controlled by electric signals at their respective control gates that are, in general, generated by the flash memory based on the status of the stored data currently being read.
The data outputs signals from the output buffer driver can be generated with the supply voltage (Vcc) or with a voltage source of a different magnitude, such as a supply voltage (VccQ). A problem occurs when the output buffer driver generates the data output signals with supply voltages that are greater than the supply voltage (Vcc). Under these conditions, the p-channel pull-up transistor may not be capable of being fully turned off due to the supply voltage at the source of the p-channel pull-up transistor being higher than a logic high electric signal generated by the flash memory with the supply voltage (Vcc). When the data output signals from the output buffer driver are switched from logic high to logic low, the data output signals will supply undesirable current as well suffer from slow switching time due to the continued partial activation of the p-channel pull-up transistor.
SUMMARY
The presently preferred embodiments include a flash memory that is capable of turning off completely a p-channel pull up transistor in an output buffer driver circuit without regard to the magnitude of the voltage source used to generate data output signals. The voltage level at the source of the p-channel pull-up transistor is about equal to an external supply voltage (VccQ). The flash memory operates with both a supply voltage (Vcc) and the external supply voltage (VccQ) to generate output signals that fully control the output buffer driver circuit. The p-channel pull-up transistor is completely deactivated when the voltage level of the electric signal applied to the control gate of the p-channel pull-up transistor is about equal to the external supply voltage (VccQ). Accordingly, the flash memory can be interfaced with electronic systems operated with an external supply voltage (VccQ) that is greater than the supply voltage (Vcc) that operates the flash memory.
The present invention discloses a memory device that is operated with a supply voltage (Vcc). The preferred memory device is a flash memory. The flash memory includes an output buffer circuit electrically connected with an output buffer driver circuit. The output buffer driver circuit is supplied an external supply voltage (VccQ). The output buffer driver circuit generates a data output signal on a data output line in response to the output buffer circuit.
The output buffer circuit includes a p-channel pull-up circuit, an n-channel pull-up circuit and a pull-down circuit to control the output buffer driver circuit. The p-channel pull-up circuit includes an activation circuit that is supplied the external supply voltage (VccQ) for generating a feedback signal when directed by the electric signals. The p-channel pull-up circuit also includes a driver circuit electrically connected with the activation circuit and the n-channel pull-up circuit that is also supplied the external supply voltage (VccQ). During operation of the flash memory, the driver circuit is responsive to the electric signals and the feedback signal to generating an output signal that is referred to as a third output signal. The third output signal controls the p-channel pull-up transistor in the output buffer driver circuit such that the p-channel pull-up transistor can be completely deactivated.
The n-channel pull-up circuit is electrically connected with the p-channel pull-up circuit and generates an output signal, which is referred to as a second output signal, when directed by the p-channel pull-up circuit. The second output signal controls the output buffer driver circuit to gene rate the data output signal. The pull-down circuit generates an output signal, which is referred to as a first output signal, when directed by the electric signals generated by the flash memory. The first output signal controls an n-channel pull-down transistor within the output buffer driver circuit.
Another preferred embodiment discloses a method of controlling generation of an output signal with an external supply voltage (VccQ) using a voltage buffer circuit in a memory device. The method comprises the steps of providing a supply voltage (Vcc) that is used by the memory device to generate electric signals. The voltage buffer circuit generates a feedback signal in response to the electric signals using the external supply voltage (VccQ). The voltage buffer circuit is responsive to the feedback signal and the electric signals to generate the output signal using the external supply voltage (VccQ).
These and other features and advantages will become apparent upon consideration of the following detailed description of the presently preferred embodiments, viewed in conjunction with the appended drawings.


REFERENCES:
patent: 5311076 (1994-05-01), Park et al.
patent: 5420525 (1995

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