Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-05-30
2004-09-07
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C326S026000, C326S082000, C327S108000, C327S379000
Reexamination Certificate
active
06788586
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output buffer for a nonvolatile memory with output signal switching noise reduction, and to a nonvolatile memory comprising the same.
2. Description of the Related Art
As is known, at present the semiconductor device market demands the manufacture of storage devices with increasingly higher operating frequencies, and this results in the need to have available output buffers with increasingly higher switching speeds.
These switching speeds are currently obtained by increasing the amplitude of the current supplied by the output buffers, and this increase in the output current is obtained by increasing the size of the output buffers.
However, the larger the sizes of the output buffers, the higher the currents that they absorb during the switching phase, and these currents consequently create sharp drops or dumps in the supply voltage of the storage devices, the dumps concurring in considerably reducing the setting time, and hence the reading time, of the storage devices.
In particular, the dumps in the supply voltage of the storage devices define the so-called “switching noise” of storage devices and are closely linked to parameters that are often not controllable, such as the inductive characteristics of the supply path, the number of output buffers that switch simultaneously, the value of the supply voltage of the storage devices, etc.
In order to reduce switching noise, numerous techniques for controlling the slew rate of output buffers have been proposed, most of which are essentially based upon the principle of limiting the time derivative of the current absorbed by the output buffers by reducing the charging and discharging speed of the gate terminals of the pull-up and pull-down transistors of the output stages of the output buffers during the turning-on of the latter.
In particular, slowing-down of charge and discharge of the gate terminals of the pull-up and pull-down transistors of the output stages of output buffers is currently obtained by acting on the logic inverters that control the pull-up and pull-down transistors in two different alternative ways: either using resistive transistors or by means of current control.
In detail, the former technique consists in rendering resistive the pull-down transistor of the logic inverter that controls the pull-up transistor of the output stage and the pull-up transistor of the logic inverter that controls the pull-down transistor of the output stage, whilst the latter technique consists in current-controlling the pull-down transistor of the logic inverter that controls the pull-up transistor of the output stage and the pull-up transistor of the logic inverter that controls the pull-down transistor of the output stage.
Although the above-mentioned techniques enable a reduction in the time derivative of the current absorbed by output buffers and an improvement in the immunity to the switching noise of output buffers, they present, however, a drawback that does not enable adequate exploitation of all their advantages.
In particular, the major undesired effect of these techniques is that of introducing a further switching delay of the output buffers in addition to the delay caused by the high capacitance typically connected to the outputs of the output buffers, this delay concurring in reducing the maximum switching speed, and hence the maximum switching frequency, of the output buffers.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention provides an output buffer for a memory device and a memory device that are free from the drawbacks described above.
According to an embodiment of the present invention an output buffer for a memory device is provided, including an output stage having a first transistor and a second transistor connected in series between a first line set at a first potential and a second line set at a second potential and having an intermediate node connected to an output of the output buffer. The output stage includes unidirectional decoupling means for decoupling the output of said output buffer from at least the first line or the second line during a switching transient of the output buffer, the decoupling means arranged in series with the first and second transistors between the first and second lines.
According to another embodiment of the present invention a memory device is also provided, including an output buffer as described above.
An embodiment of the invention provides a method, including inputting a first logic value to an input of an output buffer, inputting a second logic value, different from the first value, to the input, and, switching an output of the output buffer from the first logic value to the second logic value by decoupling the output from a first line at a first potential and coupling the output to a second line at a second potential, wherein a diode is connected between the output and the second line.
REFERENCES:
patent: 5015889 (1991-05-01), Reay
patent: 5149991 (1992-09-01), Rogers
patent: 5365123 (1994-11-01), Nakase et al.
patent: 5929669 (1999-07-01), Kim
patent: 6225838 (2001-05-01), Lee
Bedarida Lorenzo
Confalonieri Emanuele
Geraci Antonino
Sforzin Marco
Bennett II Harold H.
Jorgenson Lisa K.
Mai Son
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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