Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-05-30
2004-12-07
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230080
Reexamination Certificate
active
06829177
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output buffer for a nonvolatile memory with optimized slew-rate control.
2. Description of the Related Art
As is known, at present the semiconductor device market demands the manufacture of memory devices having increasingly higher operating frequencies, and this results in the need to have available output buffers with increasingly higher switching speeds.
These switching speeds are currently obtained by increasing the intensity of the current supplied by the output buffers, and this increase in the output current is obtained by increasing the size of the output buffers.
However, the larger the sizes of the output buffers, the higher the currents that they absorb during the switching phase, and these currents consequently create sharp drops or dumps in the supply voltage of the memory devices, these dumps concurring in considerably reducing the setting time, and hence the reading time, of the memory devices.
In particular, the dumps in the supply voltage of the memory devices define the so-called “switching noise” of memory devices and are closely linked to parameters that are often not controllable, such as the inductive characteristics of the supply path, the number of output buffers switching simultaneously, the value of the supply voltage of the memory device, etc.
In order to reduce switching noise, numerous techniques for controlling the slew rate of output buffers have been proposed, most of which are essentially based upon the principle of limiting the time derivative of the current absorbed by the output buffers by reducing the charging and discharging speed of the gate terminals of the pull-up and pull-down transistors of the output stages of the output buffers during the turning-on step of the latter.
In particular, slowing-down of charge and discharge of the gate terminals of the pull-up and pull-down transistors of the output stages of output buffers is currently obtained by acting on the logic inverters that control the pull-up and pull-down transistors in two different alternative ways: either using resistive transistors or by means of current control.
In detail, the former technique consists in rendering resistive the pull-down transistor of the logic inverter that controls the pull-up transistor of the output stage and the pull-up transistor of the logic inverter that controls the pull-down transistor of the output stage, whilst the latter technique consists in current-controlling the pull-down transistor of the logic inverter that controls the pull-up transistor of the output stage and of the pull-up transistor of the logic inverter that controls the pull-down transistor of the output stage.
Although the above-mentioned techniques enable a reduction in the time derivative of the current absorbed by output buffers and an improvement in the immunity to switching noise of output buffers, they present, however, a drawback that does not enable adequate exploitation of all their advantages.
In particular, the major undesired effect of these techniques is that of introducing a further switching delay of output buffers in addition to the delay caused by the high capacitance typically connected to the outputs of the output buffers, this delay concurring in reducing the maximum switching speed, and hence the maximum switching frequency, of output buffers.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention provides an output buffer for a memory device and a memory device that are free from the drawbacks described above.
According to an embodiment of the present invention, an output buffer for a memory device is provided. The output buffer includes an output stage formed by a pull-up transistor and a pull-down transistor connected in series between a supply line set at a supply potential and a ground line set at a ground potential. The output buffer further includes a pre-biasing stage for pre-biasing the control terminal of the pull-up transistor and a pre-biasing stage for pre-biasing the control terminal of the pull-down transistor in order to bring these transistors to the turning-on threshold.
According to another embodiment of the present invention, a memory device is also provided, including an output buffer as described above.
Another embodiment of the invention provides a method, including inputting a first logic value to an input of an output buffer, inputting a second logic value, different from the first value, to the input, switching an output of the output buffer from the first logic value to the second logic value by turning off a first transistor coupled between the output and a first line at a first potential and turning on a second transistor coupled between the output and a second line at a second potential, and biasing the first transistor at its turning-on threshold.
REFERENCES:
patent: 4570091 (1986-02-01), Yasuda et al.
patent: 5293081 (1994-03-01), Chiao et al.
patent: 5539335 (1996-07-01), Kobayashi et al.
patent: 5798970 (1998-08-01), Ong
patent: 6072354 (2000-06-01), Tachibana et al.
patent: 6141263 (2000-10-01), Protzman
Bedarida Lorenzo
Corradi Andrea
Mostola Maria
Zucchinali Massimo
Bennett II Harold H.
Elms Richard
Jorgenson Lisa K.
Nguyen Tuan T.
Seed IP Law Group PLLC
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