Output buffer circuit of semiconductor memory device

Details Output buffer circuit of semiconductor memory device Output buffer circuit of semiconductor memory device

1997-07-10

1998-08-18

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

3652335, G11C 700

Patent

active

057966613

ABSTRACT:
An output buffer circuit of a semiconductor memory device, the circuit includes an address transition detector detecting a transition of address signals, a NOR gate coupled to the address transition detector and receiving signals from the address transition detector and on output enable signal and outputting a signal having a logical NOR result, a decoder decoding the address signals, a memory unit coupled to the decoder and outputting data from the decoder, a sensing amplifier coupled to the memory unit and amplifying data outputted from the memory unit, an output data controller coupled to the NOR gate and the sensing amplifier and controlling output signals from the NOR gate and the sensing amplifier, a data output unit coupled to the pull-up unit and the output data controller and outputting data in accordance with output signals from the output data controller, a preset unit coupled to the output data controller and presetting an output terminal of the data output unit during a pulse interval of an output signal from the address transition detector, a pull-up unit coupled to the output data controller and the preset unit and pulling up a voltage of the output terminal according to the output signal from the address transition detector and the data outputted from the memory unit.

REFERENCES:
patent: 5355349 (1994-10-01), Sakata
patent: 5384735 (1995-01-01), Park et al.

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