Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2004-10-25
2009-11-03
Sorrell, Eron J (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S052000, C365S207000, C365S227000, C326S082000, C326S083000, C326S096000
Reexamination Certificate
active
07613853
ABSTRACT:
An improved output buffer having single ended as well as differential signaling capabilities, providing symmetrical outputs for differential output configurations for both synchronous and asynchronous applications, comprising: a pair of flip-flops receiving complementary input signals, a pair of transmitters each having its input connected to the output of one of the flip-flops and providing its output to an output pin, a sense block that senses the transition on complementary input signals and generates a pulse at each transition, and a multiplexer having its output connected to the clock input of said pair of flip flop and one input connected to the output of the sense block for asynchronous mode operation, the second input connected to a clock signal for synchronous mode operation and a select input that enables either asynchronous mode or synchronous mode operation.
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JEDEC Solid State Technology Association 2002, ERRATA to JEDEC Standard, JEDEC, Oct. 18, 2002, pp. 11-14.
Chauhan Rajat
Kaushik Rajesh
Graybeal Jackson LLP
Jorgensen Lisa K.
Rusyn Paul F.
Sorrell Eron J
STMicroelectronics Pvt. Ltd.
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