Output buffer circuit and semiconductor memory using the same

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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C365S100000, C365S189110

Reexamination Certificate

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10721310

ABSTRACT:
An output buffer circuit of the present invention includes a plurality of unit circuits in each of which a pull-up transistor controlled by a first input signal is connected between a high-potential power supply and common node, and a pull-down transistor controlled by a second input signal is connected between the common node and a low-potential power supply, an output terminal connected to a common connecting point of the common nodes of the plurality of unit circuits, and first resistors formed respectively between the common nodes of the plurality of unit circuits and the common connecting point.

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Japanese Office Action for Patent Application No. 344926/2002, issued Aug. 4, 2006 with English translation.

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