Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2001-10-09
2003-04-29
Nelms, David (Department: 2815)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189040, C365S189080
Reexamination Certificate
active
06556485
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having an output buffer for executing data output.
2. Description of the Background Art
Semiconductor integrated circuit devices applied to various electronics execute operations in accordance with instructions and output the resulting data signals. In such a case, the data signal output from a semiconductor integrated circuit devices are driven by an output buffer, with consideration given to an output load from a subsequent circuit receiving the data signal.
FIG. 16
is a schematic block diagram showing a configuration of a conventional semiconductor integrated circuit device
1
including output buffers.
Referring to
FIG. 16
, semiconductor integrated circuit device
1
includes an internal circuit
2
and output buffers
3
,
4
. The semiconductor integrated circuit device outputs data signals D
1
and D
2
from output nodes
5
and
6
, respectively, based on output data Dr from internal circuit
2
output in response to an operation instruction.
Data signals D
1
and D
2
are supplied to different destinations, so that output loads LD
1
and LD
2
at the respective output nodes
5
and
6
are also different from each other. Output loads LD
1
and LD
2
correspond to the line capacitance between the respective nodes and the subsequent circuits to be supplied with data signals D
1
and D
2
, the input capacitance in the respective subsequent circuits, and so forth.
Internal circuit
2
generates data level control signals Dh and Dl indicating the level of output data Dr output in response to the operation instruction. Data level control signal Dh is activated to be at a logic low level (hereinafter simply referred to as L level) when output data Dr is at a logic high level (hereinafter simply referred to as H level). On the other hand, data level control signal Dl is activated to be at the H level when output data Dr is at the L level.
Output buffers
3
and
4
drive data signals D
1
and D
2
onto output nodes
5
and
6
, respectively, in accordance with data level control signals Dh and Dl output from internal circuit
2
.
Output buffer
3
includes a P-channel transistor
7
a
and an N-channel transistor
7
b
. P-channel transistor
7
a
is turned on in response to the activation (to the L level) of data level control signal Dh, to form a current path between output node
5
and a power-supply voltage Vcc. N-channel transistor
7
b
is turned on in response to the activation (to the H level) of data level control signal Dl, to form a current path between output node
5
and a ground voltage Vss.
Output buffer
4
has a configuration similar to that of output buffer
3
, and includes an N-channel transistor
8
a
and a P-channel transistor
8
b
. P-channel transistor
8
a
is turned on in response to the activation (to the L level) of data level control signal Dh, to form a current path between output node
6
and power-supply voltage Vcc. N-channel transistor
8
b
is turned on in response to the activation (to the H level) of data level control signal Dl, to form a current path between output node
6
and ground voltage Vss.
In each of output buffers
3
and
4
, the amount of current on the current path formed between a voltage according to the level of output data Dr and the associated output node
5
or
6
, i.e. a current drivability of an output buffer, corresponds to the sizes of the transistors constituting each output buffer.
FIGS. 17A and 17B
each schematically shows a relationship between the current drivability of an output buffer and a change in the voltage of a data signal.
In
FIGS. 17A and 17B
, an example of a voltage change of output node
5
is shown, in which output buffer
3
outputs data signal D
1
of the H level.
FIG. 17A
illustrates a waveform in the case where the current drivability of the output buffer is small with respect to the output load. Referring to
FIG. 17A
, at time ta, data level control signal Dh is activated to be at the L level in order to set data signal D
1
to be at the H level. In response to the activation, P-channel transistor
7
a
within output buffer
3
forms a current path between power-supply voltage Vcc and output node
5
with a current drivability corresponding to the size of the transistor.
However, when the size of P-channel transistor
7
a
is small and thus the current drivability of the output buffer is small with respect to output load LD
1
, the voltage of output node
5
is increased in a gentle slope, requiring relatively long time period &Dgr;t1 before the voltage of output node
5
exceeds a predetermined voltage Vr corresponding to the H level data at time tb.
Thus, if the current drivability of the output buffer is excessively small, the voltage of output node
5
cannot change rapidly, reducing the speed of the data output, and hence the specification such as access time may not be satisfied.
Whereas, in
FIG. 17B
, a waveform in the case where the current drivability of the output buffer is excessively large with respect to the output load. Referring to
FIG. 17B
, at time ta, data level control signal Dh is activated to be at the L level. In response to the activation, P-channel transistor
7
b
within output buffer
3
forms a current path between ground voltage Vss and output node
5
with a current drivability corresponding to the size of the transistor.
However, when the size of P-channel transistor
7
b
is large and thus the current drivability of the output buffer is excessively large with respect to output load LD
1
, the voltage of output node
5
is rapidly increased. Therefore, time period &Dgr;t2 needed before the voltage of output node
5
exceeds predetermined voltage Vr at time tc is shortened, allowing a high-speed data output. However, such a rapid change in the voltage involving an overshoot or undershoot may generate noise, which would adversely affect the operation of a subsequent circuit.
Therefore, it is necessary to design the current drivability of each output buffer to be at an appropriate value in accordance with a corresponding output load, so as not to cause the action as shown in
FIGS. 17A and 17B
.
Referring again to
FIG. 16
, in the conventional semiconductor integrated circuit device
1
, in order to change the current drivability of each of output buffers
3
and
4
, the sizes of transistors
7
a
,
7
b
,
8
a
and
8
b
constituting the output buffers must be changed, which involves a design change or mask revision at manufacturing of the device. Thus, enormous cost and time are needed for adjustment of the current drivability of the output buffer.
In order to solve such problems and to make the current drivability of the output buffer easily adjustable, Japanese Patent Laying-Open No. 7-38408 (hereinafter also referred to as Document 1) discloses, in
FIGS. 2 and 3
, the configuration of an output buffer using a plurality of transistors connected in parallel.
The output buffer shown in
FIG. 2
of Document 1 includes a plurality of transistors arranged in parallel with each other for supplying current to an output terminal, and a plurality of fuse units respectively connected between the gates of these transistors and an input terminal. Such an arrangement allows adjustment of the amount of driving current of the output buffer, by adjusting the number of activated transistors by cutting-off of the fuse units.
However, the arrangement of the output buffer shown in
FIG. 2
of Document 1 has a problem of positioning of the fuse units. If the fuse units are arranged in a region adjacent to transistor elements constituting the output buffer, constraint in the layout design will be severe. Moreover, increase of the level of a blow input for ensuring cut-off of the fuse units may adversely affect the circuit portion of the output buffer.
If, on the other hand, the fuse units are concentrated in a specific region to ensure both secure cutting-off of the fuse units an
Sato Hirotoshi
Shimizu Tadayuki
Tsukude Masaki
Le Thong
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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