Output buffer and synchronizer

Details Output buffer and synchronizer Output buffer and synchronizer

1993-12-16

1995-06-13

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518908, 326 62, G11C 700

Patent

active

054249830

ABSTRACT:
The present invention relates to an output buffer for driving an output driver of a random access memory (RAM) circuit to either of opposite binary data values from a data source and a clock wherein the relative timing of data and clock signals is variable or uncertain, comprised of a source of data signals having pulses one of which has a rising edge either being earlier than a leading edge of a data pulse, being later than the leading edge of the data pul se, or being in a race condition with the data pulse, a source of data signals, a latency counter for receiving the clock signals and for outputting a latent control, apparatus for summing the latent clock signal and the data pulse, and apparatus for providing a signal to an output driver from the summing apparatus which is in sync with the latent clock signal.

REFERENCES:
patent: 5087840 (1992-02-01), Davies et al.
patent: 5305271 (1994-04-01), Watanabe

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