Outer buried contact region connecting drain region to inner bur

Details Outer buried contact region connecting drain region to inner bur Outer buried contact region connecting drain region to inner bur

1997-09-26

1999-05-11

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257377, 257379, 257385, 257904, H01L29/76;27/11

Patent

active

059030356

ABSTRACT:
An FET semiconductor substrate includes source/drain regions with an outer buried contact region overlapping the drain region, a gate oxide layer, and a polysilicon layer over the gate oxide layer. An inner buried contact opening through the polysilicon and the gate oxide layer reaches down to the substrate over the outer buried contact region. An inner buried contact region, within the outer buried contact region, is self-aligned with the buried contact opening. A second polysilicon layer formed over the gate oxide layer reaches down through the buried contact opening into contact with the inner buried contact region. An interconnect and a gate electrode are formed from the polysilicon layers. Source/drain regions are self-aligned with the gate electrode and whereas the drain region is spaced from the inner buried contact region, the outer buried contact region interconnects the drain region with the inner buried contact region.

REFERENCES:
patent: 4792841 (1988-12-01), Nagasawa et al.
patent: 5187566 (1993-02-01), Yoshikawa et al.
patent: 5412237 (1995-05-01), Komori et al.
patent: 5451534 (1995-09-01), Yang
patent: 5486717 (1996-01-01), Kokubo et al.
patent: 5780887 (1998-07-01), Nakagawa et al.

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