Out-of-band look-ahead arbitration method and/or architecture

Details Out-of-band look-ahead arbitration method and/or architecture Out-of-band look-ahead arbitration method and/or architecture

2000-12-08

2004-03-30

Auve, Glenn A. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S309000

Reexamination Certificate

active

06715021

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for transferring data bus control between multiple devices generally and, more particularly, to a method and/or architecture for out-of-band look-ahead arbitration for transferring data bus control between multiple devices in a queue expanded mode without a clock cycle penalty.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a conventional system
10
for implementing multiqueue first-in first-out (FIFO) devices is shown. The system
10
includes a selector section
12
, a selector section
14
and a number of memory sections
16
a
-
16
n
. The memory sections
16
a
-
16
n
are each implemented as FIFO devices. The conventional system
10
implements each of the FIFOs
16
a
-
16
n
as an independent physical memory.
The selector section
12
receives data from a write interface and presents the data to one of the memory sections
16
a
-
16
n
in response to a write select signal WR_SEL. The selector section
12
selects one of the FIFOs
16
a
-
16
n
based on the signal WR_SEL. The incoming data is then stored into the appropriate FIFO
16
a
-
16
n
. Similarly, the selector section
14
presents data to a read interface from one of the memory sections
16
a
-
16
n
in response to a read select signal RD_SEL. The selector section
14
selects one of the FIFOs
16
a
-
16
n
based on the signal RD_SEL and reads the data from the appropriate FIFO
16
a
-
16
n.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a plurality of storage devices and a scheduler circuit. Each of the plurality of storage devices may be configured to store and present one or more packets of a data stream over one or more first busses operating at a first speed. The scheduler circuit may be configured to determine which of the plurality of storage devices transmits the packets of the data stream. A second bus that may be configured to synchronize the plurality of devices. The second bus may operate at a second speed.
The objects, features and advantages of the present invention include providing a method and/or architecture for out-of-band look-ahead arbitration that may (i) implement an event driven variable stage pipeline system; (ii) operate with a plurality of clocks; (iii) have a minimum block size less than total round-time delay; (iv) implement a system where the devices that can arbitrate in the same order as that of queue address, which may select the devices randomly; (v) be implemented without an external arbiter; (vi) allow proper communication between the devices, where the communication may be a function of the packet size; (vii) change the latency of the packets according to the size of the packet being processed; (viii) handle (a) any packet size and/or (b) back-to-back reads; (ix) be implemented without open-drain pads; and/or (x) be implemented independently of the latency between addressing the queue and retrieving data.


REFERENCES:
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patent: 5963499 (1999-10-01), Leong et al.
patent: 6526495 (2003-02-01), Sevalia et al.
S. Babar Raza et al., “Architecture for Implementing Virtual Multiqueue FIFOS”, Ser. No. 09/676,704, Filed: Sep. 29, 2000.
S. Babar Raza et al., “Method and Logic for Storing and Extracting In-Band Multicast Port Information Stored Along with the Data in a Single Memory Without Memory Read Cycle Overhead”, Ser. No. 09/676,171, Filed: Sep. 29, 2000.
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S. Babar Raza et al., “Logic for Initializing the Depth of the Queue Pointer Memory”, Ser. No. 09/676,705, Filed: Sep. 29, 2000.
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S. Babar Raza et al., “Method and/or Architecture for Implementing Queue Expansion in Multiqueue Devices”, Ser. No. 09/714,441, Filed: Nov. 16, 2000.
Somnath Paul et al., “FIFO Read Interface Protocol”, Ser. No. 09/732,686, Filed: Dec. 8, 2000.
Somnath Paul et al., “FIFO Read Interface Protocol”, Ser. No. 09/732,685, Filed: Dec. 8, 2000.
S. Babar Raza et al., “Logic for Providing Arbitration for Synchronous Dual-Port Memory”, Ser. No. 09/676,169, Filed: Sep. 29, 2000.
Jiann-Cheng Chen et al., “Configurable Fast Clock Detection Logic with Programmable Resolution”, Ser. No. 09/775,372, Filed: Feb. 1, 2001.

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