Orientation independent oxidation of nitrided silicon

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S424000, C438S440000, C438S445000, C438S770000

Reexamination Certificate

active

06727142

ABSTRACT:

TECHNICAL FIELD
The field of the invention is that of silicon semiconductor processing, in particular forming vertical CMOS transistors.
BACKGROUND OF THE INVENTION
In the constant drive to save space, advanced CMOS processing techniques now include CMOS transistors that are oriented vertically. When a trench is etched into a silicon substrate, a transistor formed in the trench with a vertical orientation will have its gate exposed to two different crystal orientations, and it is known in the art that oxide grows at distinctly different rates on the <100> and <110> crystal planes. The difference in growth rates on these planes typically ranges between 40% and 100%.
It has been reported in U.S. Pat. No. 6,358,867 that a growth ratio of 0.9 for the <100> and <110> planes has been achieved using a low pressure mixture of hydrogen and oxygen.
This improvement still falls short of the ideal goal of equal growth rates, which will result in still better quality transistors and other structures formed on complex multi-crystal orientation surfaces.
The art still needs an improved method of growing high-quality oxide on complex surfaces of silicon having at least two crystallographic orientations.
SUMMARY OF THE INVENTION
The invention relates to a method of growing oxide on a complex surface that achieves a ratio of growth rates of 99%.
A feature of the invention is that a small ratio of nitride thickness to final oxide thickness is preferred.
A feature of the invention is the use of a prebake step in a nitrogen-containing ambient.
Another feature of the invention is nitride deposition with the use of an ammonia ambient at an elevated temperature.
Another feature of the invention is a prebake temperature range of between 500° C. and 1100° C.


REFERENCES:
patent: 5047359 (1991-09-01), Nagatomo
patent: 5940718 (1999-08-01), Ibok et al.
patent: 6201276 (2001-03-01), Agarwal et al.
patent: 6214670 (2001-04-01), Shih et al.
patent: 6348388 (2002-02-01), Faltermeier et al.
patent: 6358867 (2002-03-01), Tews et al.
patent: 6362040 (2002-03-01), Tews et al.
Pending application-09/874,144, filed Jun. 5 2001, group are 2812, entitled “Oxidation of silicon nitride films in semiconductor devices”.
Lin et al., “Effects of post-deposition anneal on the electrical properties of Si3N4 gate dielectric”, IEEE Electron Device Letters, vol. 23, No. 3, Mar. 2002, pp. 124-126.

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