Optimized flash memory cell

Details Optimized flash memory cell Optimized flash memory cell

2001-07-13

2004-03-16

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C257S314000, C257S315000, C257S316000

Reexamination Certificate

active

06706594

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor fabrication processing and, more particularly, to a fabrication method for forming storage cells in semiconductor devices, such as non-volatile flash memory devices.
BACKGROUND OF THE INVENTION
Non-volatile semiconductor memory devices are currently used extensively through the electronics industry. One type of non-volatile semiconductor memory devices employs the use of floating gate memory cells that are able to retain and transfer charge through a variety of mechanisms which include avalanche injection, channel injection, tunneling, etc. A flash memory device is such a semiconductor device that utilizes a floating gate memory cell. As is the case with most semiconductors being fabricated, the industry continues to push for smaller devices that contain a larger number of memory cells than each previous generation. This is also the case for the flash memory device.
In a flash memory device, fabrication of the components that make up the floating gate transistor determines the ability of the device to be programmed and retain an electrical charge as well as the ability of the device to be reprogrammed by being erased (or the removal of the electrical charge). Flash memory cells comprising floating gate transistors are laid out in such a manner that a plurality of cells forms a memory array.
A device in the programmed state, i.e., charge stored on the floating gate, represents a stored “0” and a device in the non-programmed state, i.e., no charge stored on the floating gate, represents a stored “1.” Reading a device in the programmed state will cause the device to conduct heavily, while reading a device in the non-programmed state the device will not conduct. Each floating gate transistor in the array has a common source line and the common source line requires sophisticated fabrication techniques.
The present invention provides a flash memory cell structure and method to fabricate a floating gate device having a self-aligned floating gate, a low resistant local interconnect to the source and a self-aligned drain electrode contact plug, all of which will provide enhanced operation of a flash memory cell device.
SUMMARY OF THE INVENTION
Exemplary implementations of the present invention include a flash memory device and processes to fabricate a flash memory device.
A first exemplary implementation of the present invention includes a flash memory device comprising a series of floating gate devices each having a floating gate self-aligned to a respective transistor gate electrode. The sources for each transistor gate are implanted so that they are interconnected by a common conductively doped active area. A metal interconnect runs a major length of interconnected source electrodes and makes substantially continuous contact therebetween. The metal interconnect may comprise a tungsten-based metal, such as tungsten/titanium. A metal self-aligned drain connecting to a respective drain may be comprised of tungsten/titanium as well.
A second exemplary implementation of the present invention includes process steps for forming a flash memory device on a semiconductor assembly by forming a series of floating gate devices, each having floating gate electrodes self-aligned to their respective transistor gate electrode. Implanted source electrodes connected together by a conductively doped active area are formed. Then, a nitride barrier layer is formed such that it overlies each transistor gate. Next, a planarized insulation layer is formed over the nitride barrier layer. Portions of the planarized insulation layer are removed while using the nitride barrier layer to self-align an interconnect via to underlying source electrodes.
Next, a metal local interconnect is formed into the interconnect via. The metal interconnect runs the major length of the source electrodes, while making contact therebetween. It is optional to simultaneously form metal drain plugs for each floating gate device and self-aligning each metal drain plug to an underlying drain electrode. The metal interconnect and the metal drain plug may be formed from a tungsten-based metal, such as tungsten/titanium.


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