Optimized-delay multiplexer

Details Optimized-delay multiplexer Optimized-delay multiplexer

1999-05-13

2004-06-29

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C326S113000, C327S408000

Reexamination Certificate

active

06756820

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a multiplexer with an optimized delay. The multiplexer comprises at least two pass elements which can each be driven via a first path by a control signal directly, and via a second path by the control signal inverted by an inverter.
Multiplexers and demultiplexers are usually produced using tristate inverters or pass elements or NAND gates. Tristate inverters in this context are inverters which have three states, namely “1”, “0” and “high resistance.”
FIG. 3
illustrates an exemplary embodiment of a prior art demultiplexer with pass or transfer elements
1
,
2
and an inverter
3
. The pass element
1
comprises an n-channel MOS transistor
4
and a p-channel MOS transistor
5
. Similarly, the pass element
2
comprises an n-channel MOS transistor
6
and a p-channel MOS transistor
7
. The transistors
4
and
5
are connected in parallel with one another, as are the transistors
6
and
7
. A first input signal IN
1
is fed via the source-to-drain path of the transistors
4
,
5
, while a second input signal IN
2
is fed via the source-to-drain path of the transistors
6
and
7
. The outputs of the two pass elements
1
,
2
are connected to a common output node OUT. The gates of the transistors
5
,
6
are driven by a control signal C
2
which is equivalent to a control signal CTRL. The gates of the transistors
4
,
7
are driven by a control signal C
1
obtained from the control signal CTRL via the inverter
3
. This means that the control signals C
1
and C
2
are inverted with respect to one another.
When, in the demultiplexer shown in
FIG. 3
, the control signal C
1
is at “
0
”, then the transistor
4
is on, while the transistor
7
is off. In this case, the control signal C
2
is at “
1
”, which means that the transistor
5
is on, while the transistor
6
is off. In other words, when the control signal CTRL is at “
1
”, the pass element
2
is on, while the pass element
1
is off.
In the circuit arrangement shown in
FIG. 3
, the addition of the inverter
3
now causes the signal C
1
to be somewhat delayed in relation to the signal C
2
, because it has to pass through the inverter
3
. In other words, in the circuit arrangement shown in
FIG. 3
, the pass elements
1
,
2
are each driven at different speeds, which is a disadvantage for time-critical applications of the multiplexer or demultiplexer, because, due to the fact driving occurs at different times, the input signals IN
1
and IN
2
are supplied to the output OUT with the same delay.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an optimized-delay multiplexer or demultiplexer, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which is capable of providing a time-synchronous output signal for time-critical applications as well.
With the foregoing and other objects in view there is provided, in accordance with the invention, an optimized-delay multiplexer or demultiplexer, comprising:
a first path carrying a control signal and a second path receiving the control signal;
an inverter connected in the second path for inverting the control signal and forming an inverted control signal;
a first pass element connected in the first path and driven by the control signal directly;
a second pass element connected in the second path and driven by the inverted control signal; and
a third pass element connected in the first path for simulating a delay caused by the inverter.
In accordance with an added feature of the invention, the first pass element has an input receiving an input signal and the second pass element has an input receiving an input signal separate from the input signal of the first pass element.
In accordance with an additional feature of the invention, the first pass element has an input receiving an input signal and the second pass element has an input receiving the input signal in an inverted state.
In accordance with a concomitant feature of the invention, the first, second, and third pass elements each include an n-channel MOS transistor and a p-channel MOS transistor connected in parallel with the n-channel MOS transistors.
In other words, the above-noted objects of the invention are satisfied with a multiplexer of the type mentioned in the introduction in which the first control path is provided with an additional pass element which simulates the delay caused by the inverter.
Hence, the optimized-delay multiplexer (or demultiplexer) according to the invention uses an additional optimized pass element in the path of the control signal which is not provided with an inverter. The additional pass element simulates the time delay inevitably introduced by the inverter, so that the respective control signals arrive at the pass elements simultaneously.
It has also been found that pass elements are generally more suitable as “switches” than are tristate inverters, if the latter are observed using a process window. Tristate inverters are active or amplifying switches in which process fluctuations have a much more pronounced effect on the switching speed than on “passive” pass elements. Thus, in a poor p-channel FET, the rising output edge is slow, whereas this is the falling output edge in the case of an n-channel FET. This means that the variation of pass elements obtained from a wafer is smaller than process-related fluctuations during the manufacture of tristate inverters.
The inertia of the pass elements during switching also causes an output signal to be produced which is delayed uniformly with respect to the control signal, even if the individual control signals for the respective pass elements do not switch at exactly the same instant.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an optimized-delay multiplexer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.


REFERENCES:
patent: 5233233 (1993-08-01), Inoue et al.
patent: 5625303 (1997-04-01), Jamshidi
patent: 5955912 (1999-09-01), Ko
patent: 5973507 (1999-10-01), Yamazaki
patent: 0647030 (1995-04-01), None
patent: 61-195126 (1986-12-01), None
patent: 8-76976 (1996-03-01), None

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