Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1999-02-16
2001-04-10
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S737000, C257S693000, C257S786000, C257S698000
Reexamination Certificate
active
06215184
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of laying out traces on a substrate and the layout for connection of a semiconductor chip to a printed wiring board and the like.
2. Brief Description of the Prior Art
Semiconductor integrated circuits are formed in semiconductor chips which contain the electrical circuits. Bond pads are generally disposed on the chip with the chip being mounted within a package and the bond pads being connected by wires to lead frame fingers or the like which extend externally of the chip. The package, after fabrication, is generally secured to a printed wiring board with the lead frame fingers or the like connected to bonding regions on the printed wiring board. The package as well as the electrically conductive members which transfer the signals from the chip to the printed wiring board add to the undesirable loads (i.e., inductances, noise, crosstalk, etc.) which the chip may see with the magnitude of these undesirable loads increasing with increasing chip operating frequency.
A typical package may include a substrate having a cavity which contains a chip within the depression. Bond wires couple bond pads on the chip to individual copper traces on the substrate, the copper traces each extending to an electrically conductive aperture or via which extends through the substrate to an electrically conductive ball pad and a solder ball. The vias and ball pads are formed in a matrix array having plural rows and columns of vias which are located adjacent one or more of the sides defining the depression. Adjacent vias and ball pad centers in a row or a column are spaced apart from each other by a distance defined herein as a “ball pitch”, this distance being the dimension from the center of one via or ball pad to the center of the adjacent via or ball pad in the same row or in the same column. The “ball pitch” between all adjacent vias or ball pads in the same row or in the same column is the same. The solder ball is soldered to a pad on a printed wiring board in standard manner as discussed in the above noted copending application to make the connection from the chip to the printed wiring board pad.
The copper traces as well as the bond wires, electrically conductive regions in the vias and surrounding wiring and packaging add additional circuitry to the electrical circuit which bring to the circuit additional resistances, inductances and capacitances. The layout of the circuitry and especially the layout of the traces materially affects the performance of the chip, this being particularly material in the case of differential wiring pairs wherein pairs of wires carry the same or similar signals but are out of phase with each other. It is therefore apparent that a layout is highly desirable which minimizes the above noted problems of the prior art.
SUMMARY OF THE INVENTION
In accordance with the present invention, the above described problems of the prior art are minimized.
Briefly, the path traversed by each trace of each differential wiring pair is adjusted to have a pitch or distance therebetween substantially equal to or less than a ball pitch as defined hereinabove, to be parallel to each for the maximum possible distance, to each be as close as possible to the same length and to have the same cross-sectional geometry to the closest extent possible. In other words, it is a requirement that the parallel positioning of the trace portion of each differential wiring pair be maximized to the greatest possible extent and that the trace lengths be equalized to the greatest possible extent. The quality of the differential pairs is dependent upon each of (1) the degree of parallelism, (2) equality of length and (3) substantial identity of geometry and spacing between the crosssections of the two traces forming the differential pair. It is also necessary that each trace of the differential pair be equally spaced from the ground plane, if present, and be tailored to provide maximal performance with respect to the ground plane. The geometry of design is set up to match odd/even mode circuit impedance. Accordingly, the dielectric constant of the substrate separating the signal plane from the ground plane can be controlled to control the impedance in the signal lines as is well known. The geometric relationship between the width, separation, thickness and distance from the ground plane of the conductors also affects the impedance of the conductors.
In the present state of the art, it is possible to provide at most two signal traces between a pair of adjacent columns at minimum ball pitch. In order to meet the above criteria, it has been found that the above described maximization is obtained, with reference to
FIG. 4
, by connecting pairs in the manner
1
-
2
,
1
-
2
and
3
—
3
. This means that, given three adjacent columns
0
,
1
,
2
and three rows of vias
1
,
2
,
3
or connection locations in those columns, a first pair of traces will be connected to rows
1
and
2
of a column
1
with the trace connected to row
2
travelling between the columns
0
and
1
, a second pair of traces will be connected to rows
1
and
2
of column
2
with the trace connected to row
2
extending between columns
2
and
3
and a third pair of traces which pass between columns
1
and
2
and are connected to the third row in each of these columns. In the event the technology permits more than two traces to be passed between a pair of adjacent rows, the above manner of connection would be altered, as is apparent.
It should be understood that, though the above described circuit has been laid out to accommodate differential pairs, each trace of each differential pair can be used to accommodate other types of signals.
It should be understood that the above described layout of signal traces can also be provided wherein the ball grid array is disposed on the same surface as the as the signal trace layout with the vias being eliminated, similar to the embodiment of FIG.
3
and in the above referenced copending application but with the additional column and connections thereto as in the subject specification.
Advantages of the layout in accordance with the present invention are: improved electrical performance, suitability for high frequency applications and flexibility to use nearly all signal traces as differential pairs or single ended lines. Crosstalk is also substantially reduced.
REFERENCES:
patent: 5612576 (1997-03-01), Wilson et al.
patent: 5729894 (1998-03-01), Rostoker et al.
patent: 5808873 (1998-09-01), Celaya et al.
patent: 5962917 (1999-10-01), Moriyama
patent: 6008543 (1999-12-01), Iwabuchi
patent: 6013946 (2000-01-01), Lee et al.
patent: 6054767 (2000-04-01), Chia et al.
patent: 6075710 (2000-06-01), Lau
Hassanzadeh Nozar
Stearns William P.
Brady III Wade James
Clark Jhihan B
Clark Sheila V.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Optimized circuit design layout for high performance ball... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Optimized circuit design layout for high performance ball..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimized circuit design layout for high performance ball... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2528557