Optimization of routing layers and board space requirements...

Details Optimization of routing layers and board space requirements... Optimization of routing layers and board space requirements...

2006-02-28

2006-02-28

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257S691000, C257S697000, C257S698000, C361S767000, C361S777000, C174S261000, C174S262000, C174S263000

Reexamination Certificate

active

07005753

ABSTRACT:
A method, system, and apparatus for optimizing routing layers and board space requirements for a ball grid array land pattern is described. The land pattern includes a plurality of conductive pads arranged in an array of rows and columns. The array of pads has at least one edge of a perimeter of the array not fully populated with conductive pads, whereby spaces are created in the at least one edge by the missing conductive pads. The spaces create additional routing channels for signals from conductive pads within the array to be routed externally to the array through the at least one edge.

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