Optimal process flow of fabricating nitride spacer without...

Details Optimal process flow of fabricating nitride spacer without... Optimal process flow of fabricating nitride spacer without...

1999-07-06

2001-01-16

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S265000, C438S257000, C257S321000

Reexamination Certificate

active

06174772

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of forming a nitride spacer without inter-poly oxide damage in the cell.
(2) Description of the Related Art
A spacer between the floating gate and the word line (connected to the control gate) of a split gate flash memory cell is needed in order to avoid reverse tunneling, or, “write disturb” as is known in the art. However, the process of forming spacers after the forming of inter-poly oxide as currently practiced in the manufacturing line causes damage to the spacers. The amount and nature of damage varies from one cell to another on a given wafer, thus causing undesirable variations in the erasing speed of the manufactured memory devices. It is disclosed later in the embodiments of the present invention a method of forming a spacer and an additional inter-poly oxide which, together, substantially reduce such variations within a wafer as well as from wafer to wafer in the production line.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well known split-gate cell is shown in FIG.
1
. There, a MOS transistor is formed on a semiconductor substrate (
10
) having a first doped region (
11
), a second doped region (
13
), a channel region (
15
), a gate oxide (
30
), a floating gate (
40
), intergate dielectric layer (
50
) and control gate (
60
). Substrate (
10
) and channel region (
15
) have a first conductivity type, and the first (
11
) and second (
13
) doped regions have a second conductivity type that is opposite the first conductivity type.
As seen in
FIG. 1
, the first doped region, (
11
), lies within the substrate. The second doped region, (
13
), lies within substrate (
10
) and is spaced apart form the first doped region (
11
). Channel region (
15
) lies within substrate (
10
) and between first (
11
) and second (
13
) doped regions. Gate oxide layer (
30
) overlies substrate (
10
). Floating gate (
40
), to which there is no direct electrical connection, and which overlies substrate (
10
), is separated from substrate (
10
) by a thin layer of gate oxide (
30
) while control gate (
60
), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (
50
) therebetween.
In the structure shown in
FIG. 1
, control gate (
60
) overlaps the channel region, (
17
), adjacent to channel (
15
) under the floating gate, (
40
). It will be known to those skilled in the art that this structure is needed because when the cell is erased, it leaves a positive charge on the floating gate. As a result, the channel under the floating gate becomes inverted. The series MOS transistor (formed by the control gate over the channel region) is needed in order to prevent current flow from control gate to floating gate. The length of the transistor, that is the overlap of the control gate over the channel region (
17
) determines the cell performance.
To program the transistor shown in
FIG. 1
which shows the placement of gate, source and drain voltages or Vg, V
s
and V
d
, respectively, charge is transferred from substrate (
10
) through gate oxide (
30
) and is stored on floating gate (
40
) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed “on” or “off.” “Reading” of the cell's state is accomplished by applying appropriate voltages to the cell source (
11
) and drain (
13
), and to control gate (
60
), and then sensing the amount of charge on floating gate (
40
). To erase the contents of the cell, the programming process is reversed, namely, charges are removed from the floating gate by transferring them back to the substrate through the gate oxide. Electron tunneling occurs through oxide regions (
33
) and (
53
) shown in FIG.
1
.
This programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (F-N) tunneling as is well known in prior art. Basically, a sufficiently high voltage is applied to the control gate and drain while the source is grounded to create a flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin gate oxide layer by means of Fowler-Nordheim tunneling. The tunneling is achieved by raising the voltage level on the control gate to a sufficiently high value of about 12 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value larger than the threshold voltage of a logic high that would turn it on. Thus, even when a logic high is applied to the control gate, the EEPROM remains off. Since tunneling process is reversible, the floating gate can be erased by grounding the control gate and raising the drain voltage, thereby causing the stored charge on the floating gate to flow back to the substrate. Of importance in the tunneling region is the quality and the thinness of the tunneling oxide separating the floating gate from the substrate. Inadvertent reverse tunneling, or erasure, for example, may occur if the tunnel oxide is degraded, or the spacer formed between the floating gate and the control gate is poorly shaped.
In prior art, spacers are employed for various purposes. Wang in U.S. Pat. No. 5,811,853 forms a thick spacer oxide layer on top of a floating gate and the source/drain region of a substrate to prevent shorting thereinbetween in a memory cell. In U.S. Pat. No. 5,063,172, Manley teaches a circuit fabrication method that utilizes a conductive spacer to define the gate length of a series select transistor in a split-gate memory cell. Kim of U.S. Pat. No. 5,702,965, on the other hand, discloses a flash memory cell with an insulation spacer of an oxide-nitride-oxide (ONO) or ON structure formed at the sidewalls of the floating gate. Present invention discloses a different method of forming a split-gate flash memory cell where nitride spacers are formed first on a pad oxide formed on the sidewalls of a floating gate, and then the inter-poly oxide is formed thereon. In this manner, the damage to the inter-poly oxide is avoided and the variation in the thickness of the inter-poly oxide is also substantially reduced in order to prevent the variation of the erase speed of the memory cells fabricated on the same or different wafers.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a method of forming a nitride spacer through a reversal of conventional process steps in order to avoid reverse tunneling disturb in a split-gate flash memory cell.
It is another object of this invention to provide method of forming a nitride spacer without inter-poly oxide damage in a split-gate flash memory cell.
It is still another object of this invention to provide a method of preventing variations in the thickness of inter-poly oxide in order to prevent variations in the erase speed of a split-gate flash memory cell.
It is yet another object of the present invention to provide split-gate flash memory cell having a nitride spacer underlying inter-poly oxide layer in order to suppress the variations in the thickness of the inter-poly oxide.
These objects are accomplished by providing a substrate having a plurality of active and field regions defined; forming a gate oxide layer over said substrate; forming a first polysilicon layer over said gate oxide layer; forming a first nitride layer over said first polysilicon layer; patterning said first nitride layer to define a floating gate region over said first polysilicon layer; forming a poly-oxide layer over said first polysilicon layer; etching said first polysilicon layer to form a floating gate structure; forming a pad oxide layer over said substrate; forming a second nitride layer over said pad oxide laye

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