Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2005-02-16
2009-02-03
Phu, Phuong (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S376000, C375S374000, C375S375000, C369S059110, C369S059120, C368S156000
Reexamination Certificate
active
07486757
ABSTRACT:
An optical (disc) driving system including the DLL based multiphase clock generator circuit capable of generating 32 different phases from input clock having a frequency of 800 MHz or greater. The multiphase clock generator includes on a delay locked loop (DLL) having a frequency divider for outputting an N-divided clock to a first set of M voltage-controlled delay cells within a feedback loop, and further including an identical set of M voltage-controlled delay cells outside of the feedback loop for delaying the undivided clock and for outputting M multiphase clocks.An optical driver circuit of an optical driving system and a method for implementing a write-strategy for preventing “overlapping” of marks written on adjacent grooves on an optical disc. The circuit and method produce multiple write-strategy waveforms (channels) switching at a high resolution (e.g., T/32) in the Gigahertz frequency range.
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Kim Ho-young
Kim Yong-sub
F.Chau & Associates LLC
Phu Phuong
Samsung Electronics Co,. Ltd.
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