Open bit line DRAM with ultra thin body transistors

Details Open bit line DRAM with ultra thin body transistors Open bit line DRAM with ultra thin body transistors

2001-02-09

2003-03-11

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S328000

Reexamination Certificate

active

06531727

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, and in particular to open bit line DRAM with ultra thin body transistors.
BACKGROUND OF THE INVENTION
Semiconductor memories, such as dynamic random access memories (DRAMs), are widely used in computer systems for storing data. A DRAM memory cell typically includes an access field-effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. The data charges on the storage capacitor are periodically refreshed during a refresh operation.
Memory density is typically limited by a minimum lithographic feature size (F) that is imposed by lithographic processes used during fabrication. For example, the present generation of high density dynamic random access memories (DRAMs), which are capable of storing 256 Megabits of data, require an area of 8 F
2
per bit of data. There is a need in the art to provide even higher density memories in order to further increase data storage capacity and reduce manufacturing costs. Increasing the data storage capacity of semiconductor memories requires a reduction in the size of the access FET and storage capacitor of each memory cell. However, other factors, such as subthreshold leakage currents and alpha-particle induced soft errors, require that larger storage capacitors be used. Thus, there is a need in the art to increase memory density while allowing the use of storage capacitors that provide sufficient immunity to leakage currents and soft errors. There is also a need in the broader integrated circuit art for dense structures and fabrication techniques.
As the density requirements become higher and higher in gigabit DRAMs and beyond, it becomes more and more crucial to minimize cell area. One possible DRAM architecture is the open bit line structure.
The continuous scaling, however, of MOSFET technology to the deep submicron region where channel lengths are less than 0.1 micron, 100 nm, or 1000 A causes significant problems in the conventional transistor structures. As shown in
FIG. 1
, junction depths should be much less than the channel length of 1000 A, or this implies junction depths of a few hundred Angstroms. Such shallow junctions are difficult to form by conventional implantation and diffusion techniques. Extremely high levels of channel doping are required to suppress short-channel effects such as drain-induced barrier lowering; threshold voltage roll off, and sub-threshold conduction. Sub-threshold conduction is particularly problematic in DRAM technology as it reduces the charge storage retention time on the capacitor cells. These extremely high doping levels result in increased leakage and reduced carrier mobility. Thus making the channel shorter to improve performance is negated by lower carrier mobility.
Therefore, there is a need in the art to provide improved memory densities while avoiding the deleterious effects of short-channel effects such as drain-induced barrier lowering; threshold voltage roll off, and sub-threshold conduction, increased leakage and reduced carrier mobility. At the same time charge storage retention time must be maintained.
SUMMARY OF THE INVENTION
The above mentioned problems with semiconductor memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Systems and methods are provided for transistors with ultra thin bodies, or transistors where the surface space charge region scales down as other transistor dimensions scale down.
In one embodiment of the present invention, an open bit line DRAM device is provided. The open bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. The pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer. In each memory cell a single crystalline vertical transistor is formed along side of the pillar. The single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions, and a gate opposing the vertical body region and separated therefrom by a gate oxide. A plurality of buried bit lines are formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells. Also, a plurality of word lines are included. Each word line is disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to the trench.
The invention also provides a method of fabricating an open bit line DRAM device. The method includes forming an array of memory cells. According to the teachings of the present invention forming each memory cell in the array of memory cells includes forming a pillar extending outwardly from a semiconductor substrate. Forming the pillar includes forming a single crystalline first contact layer of a first conductivity type and forming a single crystalline second contact layer of the first conductivity type vertically separated by an oxide layer.
Forming each memory cell in the array of memory cells further includes forming a single crystalline vertical transistor along side of the pillar. Forming the single crystalline vertical transistor includes depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave only on sidewalls of the pillars. Forming the single crystalline vertical transistor includes annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type. According to the teachings of the present invention, annealing causes the single crystalline first and second contact layers of a first conductivity type to seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by the now single crystalline vertically oriented material of the second conductivity type. Forming the single crystalline vertical transistor further includes forming a gate opposing the single crystalline vertically oriented material of the second conductivity type which is separated therefrom by a gate oxide.
Forming each memory cell in the array of memory cells further includes forming a plurality of buried bit lines of single crystalline semiconductor material which are disposed below the pillars in the array memory cells such that each one of the plurality of buried bit lines couples to the first contact layer of column adjacent pillars in the array of memory cells. The method further includes forming a plurality of word lines disposed orthogonally to the plurality of buried bit lines. Forming the plurality of word lines includes forming each one of the plurality of wordlines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to the trench.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following des

Affiliated with

Also associated with

Rating

Open bit line DRAM with ultra thin body transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Open bit line DRAM with ultra thin body transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Open bit line DRAM with ultra thin body transistors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3051598