Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-02-14
2004-10-05
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06800527
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory device and a method for production of the same, more particularly relates to an OTP (one time programmable) semiconductor nonvolatile memory device capable of being written with data only one time and a method for production of the same.
2. Description of the Related Art
As nonvolatile semiconductor memory devices, floating gate type, MNOS type, MONOS type, and other flash memories having various characteristics and capable of erasing data together have been developed. They have CMOS transistors as decoders and other peripheral transistors of memory cell arrays.
However, a flash memory has had a problem in that about 20 to 30 masks were necessary for producing the same, so the manufacturing cost was high.
On the other hand, as a read only memory device capable of being written with data only one time (OTPROM (read only memory)), a memory cell having one transistor and one oxide film fuse has been developed. This is disclosed in for example Japanese Examined Patent Publication (Kokoku) No. 4-9388, Japanese Examined Patent Publication (Kokoku) No. 58-28750, or Japanese Examined Patent Publication (Kokoku) No. 63-22073.
For example, Japanese Examined Patent Publication (Kokoku) No. 4-9388 discloses a memory cell having a structure shown in FIG.
1
.
For example, a gate electrode
104
is formed on a channel forming region
102
of a p-type semiconductor substrate
101
via a gate insulating film
103
, and a source region
105
and a drain region
106
containing n-type impurities are formed in the semiconductor substrate
101
on the two sides thereof, whereby a MOS field-effect transistor is formed.
An insulating film
110
of silicon oxide is formed covering the MOS transistor, contact holes reaching the gate electrode
104
, source region
105
, and the drain region
106
are formed, and a gate interconnection
115
, source interconnection
116
, and a drain interconnection
117
made of for example aluminum are filled in the contact holes.
Here, a silicon oxide film
114
is formed at an interface between the source region
105
and the drain interconnection
116
and insulates the two.
In a memory cell having the above structure, by applying a high voltage between the source region
105
and the source interconnection
116
according to the data to be written, the insulation in the silicon oxide film
114
is broken and the source region
105
and the source interconnection
116
are made conductive. Thus, data can be stored by conduction or nonconduction between the source region
105
and the source interconnection
116
in each memory cell.
Also, Japanese Examined Patent Publication (Kokoku) No. 58-28750 and Japanese Examined Patent Publication (Kokoku) No. 63-22073 disclose memory cells having structures shown in FIG.
2
and
FIG. 3
are disclosed.
These are substantially the same as the memory cell having the structure shown in
FIG. 1
, but a polysilicon layer
120
is formed connected to the source region
105
, and the source interconnection
116
is formed at an upper layer thereof via the silicon oxide film
114
.
Also, in
FIG. 2
, the polysilicon layer
120
is formed also in the drain region
106
, and the drain interconnection
117
is formed at an upper layer thereof.
In a memory cell having the above structure as well, by applying a high voltage between the source region
105
and the source interconnection
116
according to the data to be written, the insulation in the silicon oxide film
114
is broken and the source region
105
and the source interconnection
116
are made conductive. Thus, data can be stored by conduction or nonconduction between the source region
105
and the source interconnection
116
in each memory cell.
On the other hand, U.S. Pat. No. 6,034,882 discloses a semiconductor nonvolatile memory device having a memory cell array and having a peripheral circuit shown in an equivalent circuit diagram of FIG.
4
A.
Namely, as shown in
FIG. 4A
memory cells M are provided at intersecting points of conductive layers (C
1
, C
3
, C
5
, C
7
) receiving layer selection signals LSS by a switching transistor SWT controlled by a row decoder RD and conductive layers (C
2
, C
4
, C
6
) acting as the bit lines BL.
The above memory cell has a structure shown in for example FIG.
4
B.
Namely, a p
+
type polysilicon layer
202
is formed on a conductive layer
201
forming the conductive layers (C
1
, C
3
, C
5
, C
7
), and an n-type polysilicon layer
203
is formed at an upper layer thereof to thereby form a diode. A silicon oxide film
204
is formed at an upper layer of the polysilicon layer
203
, an n
+
type polysilicon layer
205
is formed at an upper layer thereof, and a conductive layer
206
forming the conductive layers (C
2
, C
4
, C
6
) is laid at an upper layer thereof.
Here, the polysilicon layer
203
and the polysilicon layer
205
are insulated by the silicon oxide film
204
.
In a memory cell having the above structure, by applying a high voltage between the polysilicon layer
203
and the polysilicon layer
205
according to the data to be written, the insulation in the silicon oxide film
204
is broken and the polysilicon layer
203
and the polysilicon layer
205
are made conductive. Therefore, data can be stored according to existence
onexistence of the diode element in each memory cell (portion where the polysilicon layer
202
and the polysilicon layer
203
are stacked).
In a memory cell having the structure shown in
FIG. 1
to
FIG. 3
described above, however, there was a problem in reproducibility and reliability of the breakage of insulation of the silicon oxide film.
Also, the semiconductor nonvolatile memory device shown in
FIGS. 4A and 4B
is configured by memory cells each comprised of a fuse of an insulating film breakage type and a diode as an active element connected therein repeating in three dimensions. Therefore, it becomes necessary to form a silicon layer having a crystallinity required for comprising the active element in an upper layer of the interconnection made of aluminum, so there is a large influence of heat treatment upon the aluminum interconnections and accompanying major difficulties in actual production.
Further, by stacking a plurality of layers having memory cells, for example, nine layers, it is possible to increase the degree of integration and to thereby realize a reduction of the manufacturing cost per unit storage capacity of the semiconductor nonvolatile memory device, but there was a problem in that, even if N number of layers are stacked, the manufacturing cost per unit storage capacity becomes larger than 1/N due to the influence of the peripheral circuits etc., so an effect of the reduction of cost cannot be sufficiently obtained.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor nonvolatile memory device capable of improving the reproducibility and reliability of the breakage of insulation of the silicon oxide film and capable of further reducing the manufacturing cost and a method for production of the same.
To attain the above object, a semiconductor nonvolatile memory device of the present invention has at least one memory cell and is programmable one time, wherein the memory cell comprises an impurity region of a first conductivity type formed in a semiconductor substrate, a first insulating film formed on the semiconductor substrate covering the impurity region, an opening formed in the first insulating film so as to reach the impurity region, and a program portion comprising a first semiconductor layer of the first conductivity type, a second insulating film, and a second semiconductor layer of a second conductivity type, the first semiconductor layer, the second insulating film and the second semiconductor layer being successively stacked in the opening, the first semiconductor layer being formed on the impurity region, the second insulating film being changed in a conductive state in response to a
Hagiwara Yoshiaki
Kubota Michitaka
Kuroda Hideaki
Nakagawara Akira
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