One step in situ doped amorphous silicon layers used for selecti

Details One step in situ doped amorphous silicon layers used for selecti One step in situ doped amorphous silicon layers used for selecti

1998-06-25

2000-03-14

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438964, H01L 218242

Patent

active

060372192

ABSTRACT:
A process for creating a crown shaped storage node electrode, covered with an HSG silicon layer, used to increase the surface area, and thus the capacitance of, high density, DRAM designs, has been developed. The process features creating a crown shaped storage node shape, from a composite amorphous silicon layer, wherein the composite amorphous silicon layer is comprised of a heavily doped amorphous silicon layer, used to alleviate capacitance depletion phenomena, sandwiched between undoped, or lightly doped, amorphous silicon layers, used to selectively accept the overlying HSG silicon layer. The process also features the use an HF vapor pre-clean procedure, followed by an in situ, selective deposition of HSG silicon seeds, in a conventional LPCVD chamber, prior to anneal cycle used to form the HSG silicon layer.

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