Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-05-02
2004-03-02
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S303000, C438S253000, C438S396000
Reexamination Certificate
active
06700153
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to one-cylinder stack (OCS) capacitors and to methods of fabricating the same, and more particularly, the present invention relates to OCS capacitors which have been formed from a double-mold, and to methods of fabricating OCS capacitors using a double-mold.
2. Description of the Related Art
As semiconductor devices increase in memory cell density, the area occupied by capacitors of the memory cells has decreased. Capacitance is proportional to the dielectric constant of the capacitor dielectric and to the surface area of the capacitor electrodes. Thus, to increase capacitance, it is necessary to either select a dielectric of increased dielectric constant and/or to increase the surface area of the capacitor electrodes. However, adopting new dielectric materials is generally expensive and time-consuming in that it is often necessary to supply new manufacturing equipment, to verify the reliability of the dielectric materials, and to ensure the ability to mass produce devices having the dielectric materials. Therefore, increasing the surface area of electrodes is usually the most cost-effective means of satisfying a requirement for increased capacitance of a device having conventional dielectrics, such as dielectric (NO) layers composed of a stack of silicon nitrite and silicon oxide layers.
Hemispherical grain (HSG) electrodes are used in conventional 128-Mbit or less DRAMs to increase the effective surface area of the electrodes. However, these electrodes cannot be applied in highly integrated devices of 256-Mbit or greater because any reduction in spacing between electrodes is limited due to the presence of HSGs on the surface of the electrodes. As such, in the case of a one-cylinder stack (OCS) storage electrode, increasing the height of the electrode from 1.4 &mgr;m to 1.6 &mgr;m, for example, has generally been considered the most efficient means of increasing the capacitance thereof.
The fabrication of a conventional OCS storage electrode will now be described with reference to
FIGS. 1-6
. In particular, an OCS capacitor storage electrode having a design rule of less than 1.2 &mgr;m is typically formed using a single mold. Referring to
FIG. 1
, an etch stop layer (not shown) is formed on an interlayer insulating layer
10
having a contact plug
15
in a surface thereof, and an oxide layer (not shown) is formed to a thickness h
1
, which substantially corresponds to the desired height of an electrode. Next, the oxide layer and the etch stop layer are sequentially etched into an oxide mold
30
having an underlying etch stop
20
. In this manner, an opening
40
is defined over the contact plug
15
, thereby exposing the contact plug
15
. Then, as shown in
FIG. 2
, polysilicon is deposited on the sidewalls of the opening
40
and on the contact plug
15
so that a cylindrical electrode
50
is formed.
Reference is made to the scanning electron microscopic (SEM) photograph of FIG.
3
. As mentioned previously, to increase the capacitance in the case of highly integrated devices, it is desired to increase the height of the OCS capacitor storage electrode to 1.6 &mgr;m or greater. However, noting that etching limitations set the slope of the sidewalls of the opening
40
, if the height of the oxide mold layer is increased from h
1
to h
2
(about 1.8 &mgr;m) and a lower critical dimension (d) of the opening
40
is maintained, a bridge B (
FIGS. 2 and 3
) may be formed between neighboring OCS capacitor storage electrodes, thereby causing a twin-bit failure. In an effort to avoid twin-bit failures, the upper critical dimension (a) of the opening
40
can be reduced by reducing the lower critical dimension (d) of the opening
40
. However, this approach is disadvantageous in that the surface area at the bottom of the opening
40
is reduced, thereby reducing capacitance.
It is also noted that twin-bit failures can occur as a result of storage electrodes falling down and contacting adjacent electrodes. As such, consideration must be given to the structural integrity of the electrodes.
That is, referring now to
FIG. 4
, after separation of the storage electrodes for cell isolation has been ensured, the oxide mold
30
is removed by wet etching. During this wet etching process, an etchant can permeate into the interface between each storage electrode
50
and an etch stop
20
, thus etching the interlayer insulating layer
10
. This can weaken the foundation of the storage electrode, causing the storage electrode to tip over and contact adjacent electrodes.
FIG. 5A
is a scanning electron microscopic (SEM) photograph showing an example in which falling electrodes have resulted in a depression having an @-shaped pattern, and
FIG. 5B
is a scanning electron microscopic (SEM) photograph showing a cross-sectional side view of electrodes falling into one another.
Therefore, there is an increasing need for a new OCS capacitor structure and a method for fabricating the same in which depressions and bridging between adjacent electrodes can be effectively avoided even in the case where the capacitor height is on the order of 1.6 &mgr;m or more.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a method of fabricating a capacitor electrode includes forming an etch stop layer over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer; forming a lower mold layer over the etch stop layer, and adjusting a wet etch rate of the lower mold layer by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer; forming an upper mold layer over the surface of the lower mold layer, wherein a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer; dry etching the upper mold layer, the lower mold layer and the etch stop layer to form an opening therein which exposes at least a portion of the-surface of the contact plug; wet etching the upper mold layer and the lower mold layer so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug; and depositing a conductive material over the surface of the opening in the upper and lower mold layers, the surface portion of the etch stop layer, and an exposed surface of the conductive plug.
According to another aspect of the present invention, a method of fabricating a capacitor includes forming a lower electrode over an interlayer insulating layer, forming a dielectric layer over the lower electrode, and forming an upper electrode over the dielectric layer. Here, formation of the lower electrode includes forming an etch stop layer over a surface of the interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer; forming a lower mold layer over the etch stop layer, and adjusting a wet etch rate of the lower mold layer by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer; forming an upper mold layer over the surface of the lower mold layer, wherein a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer; dry etching the upper mold layer, the lower mold layer and the etch stop layer to form aN opening therein which exposes at least a portion of the surface of the contact plug; wet etching the upper mold layer and the lower mold layer so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug; and depositing a conductive material over the surface of the opening in the upper and lower mold layers, the surface portion of the etch stop layer, and an exposed surface of the conductive plug.
According to still another aspect of
Hwang In-Seak
Hwang Ki-Hyun
Oh Jung-Hwan
Park Jae-Young
Park Young-Wook
Eckert George
Samsung Electronics Co,. Ltd.
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